Wednesday, 2022-04-06

sadoon[m]Oh thank God, new account and I fiddled for hours just to get my rooms back01:54
sadoon[m]How's everyone01:54
*** sadoon_albader[4 <sadoon_albader[4!~sadoonhal@2001:470:69fc:105::1:efee> has left #libre-soc02:01
Veera[m]lkcl:  Hi. I tried doing python3 develop for prjxray installation, but fails with python fasm not installed. I mean at first installation run it fails to install, but subsequent invocation it succeeds. I tried installing fasm using pip3 it works. Do you mind if I do this way?06:20
programmerjakea lot of python projects aren't intended to be used with ` develop`, so `pip install .` should be fine imho06:22
Veera[m]It is that lkcl always says develop first somehow he hates pip306:27
Veera[m]pip3 is uninstallable. but install is not06:28
Veera[m]The first script I developed used pip3. But when lkcl ran he changed it to develop06:28 develop has the advantage (just like `pip install -e .`) of linking your files into python's installed packages rather than copying your files, allowing you to modify your files without needing to reinstall after every modification06:35
programmerjakeafaict and pip will install the exact same dependencies, so that part of why luke doesn't like pip (poor security practices when downloading packages) isn't any better with setup.py06:37
programmerjakeso, other than poor security practices when downloading packages, maybe the rest of why he dislikes pip is familiarity and personal preference? idk ... security is all i remember him mentioning06:40
Veera[m]But also with pip installed packages version changes. Though we can specify exactly which version we need.06:44
Veera[m]It needs more command work06:45
Veera[m]Any idea, usually when he responds to irc06:45
programmerjakehmm, he'll probably respond when he wakes up, in 2-5hr07:02 ends up unfortunately calling pip3 which is extremely bad security practice given that is a central point of failure, a high-value hacking target, and there's absolutely no GPG-signing of packages.11:17
lkclmultiple levels of compromise11:18
lkclVeera[m] i don't "hate" it - that's assigning an irrational emotion to a logical analysis of security risk.11:19
lkclthen there is also the fact that arbitrary and random versions of software get installed, without consent.11:19
lkclthat _is_ particularly irritating11:19
lkclVeera[m], if you've got a solution that "gets the job done", then go for it, as long as it's documented why it's being done11:20
lkclsadoon[m], yeah good11:20
lkclwhat's with the new account?11:31
lkclVeera: once you're in to cerberus, just "ssh silicon".11:43
lkcli've added you to sudoers with no password needed11:44
lkcland i've set up an /etc/udev/rules.d entry to make the ft232 uart on the arty permissions 066611:45
lkclthere's an existing schroot nextpnr-xilinx, if you can leave that there (it works, so doesn't need breaking :)11:46
Veera[m]lkcl: I can login to silicon, but could not find any further what to do. So schroot will work. I will try!11:56
Veera[m]so how to load the final bitstream to arty?11:57
Veera[m]Do we have to scp the bitstream to server and using loader program the uart?11:58
lkcl"xc3sprog -c nexys4 top.bit" is the command that's already encoded into nmigen12:08
lkclyou can see that iin.... 1 sec...12:08
lkclwhere the heck is it...12:10
lkclah _ha_
lkclpull up 2 ssh terminals and run "minicom -D /dev/ttyUSB1" in one of them12:11
lkclthen in the other, schroot -c nextpnr-xilinx12:11
lkclsudo bash12:11
lkclsu - coriolis212:11
lkcl*then* schroot12:11
lkclcd src12:12
lkclcd ls212:12
lkclcd build12:12
lkclthen run that xc3sprog command12:13
lkclback on the 2nd ssh terminal running minicom you should see the microwatt hello12:14
lkclbtw if "pip3 install ." *and then* "python3 develop" does the trick, then pffh, great, don't worry about it.12:17
Veera[m]Ok. I will give a try.12:38
lkclremember i modified nmigen to match the locations /usr/local/nextpnr-xilinx/etc.etc so you don't need to adjust the script for that12:40
lkcloleee!  QuadSPI also works on Arty A7!12:46
Veera[m]yey. hyperram left?12:50
lkcldone already!12:53
lkclso it's now down to flashing the microwatt-5.7 linux kernel / initramfs into the right place, and writing some coldboot firmware to start running12:59
lkcli.e. copy from QSPI into HyperRAM then jump to it13:00
lkclprogrammerjake, i can't recall exactly where you mentioned about bext / bdep, but they're in v3.1 (p106) as Scalar ops13:15
lkclor were you referring to bit-to-byte-permute?13:15
lkclannoyingly i didn't note the VSX instruction which implements it, i only snapshotted the pseudocode. sigh13:32
sadoon[m]<lkcl> "what's with the new account?" <- I didn't like how was abusing their power as the default homeserver to ban people from other legitimate homeservers from joining rooms hosted on their network. Very scummy move.15:46
sadoon[m]Found a seemingly good one that's also not banned from joining rooms :)15:47
sadoon[m]And doesn't seem to be active politically in either which direction15:47
programmerjakelkcl: i was just relying on what says:16:01
programmerjake> vpdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p10616:01
programmerjakeit seemed to imply that vpdepd is the only OpenPower bdep instruction16:03
programmerjakeso, if that's not the case, it needs to be rephrased since it's confusing16:03
tplatenThe hello_world program reaches main and console_init, then it gets to putchar17:57
tplatenMicrowatt has two types of uarts: a standard one and a potato one17:58
lkcltplaten, yes, SYSCON determines which one it is18:04
lkclSYSCON is just "some registers addressable through wishbone"18:05
lkclwhich have SYStem CONfiguration information such as18:05
lkcl"do i have a UART0? if so what type?"18:05
lkcl"do i have BRAM?"18:05
lkcl"do i have SPI Flash?"18:05
lkcl"what is my SYS_CLK frequency?"18:05
lkcllook in include/microwatt_soc.h and search for SYSCON to match up18:07
lkclalso, use this command to get the raw assembler18:08
lkclpowerpc64le-linux-gnu-objdump -D coldboot.elf > coldboot.as18:08
lkclthen you can check the PC and INSN from the GTKWAVE trace against actual assembler listings18:08
lkclprogrammerjake, got it, yes, should be pdepd and pextd not vpdepd18:09
tplatenI'll have a look at syscon.vhdl18:14
ghostmansdHi folks, how are you?19:12
ghostmansdLong time no see19:12
ghostmansdI _hope_ in the nearest time I'd be able to finally dedicate some time to binutils19:13
ghostmansdIn fact, I've started checking where I had stopped before, and, truth to be told, it takes time to recall what I did :-)19:13
lkclghostmansd, hey good to see you're back19:21
lkclyyeah that's electrical-vs-chemical memory / neurochemistry19:22
lkclovernight transfer. tomorrow you'll be fine :)19:22
ghostmansdI'm kinda stuck at fields processing for now, e.g. mapping `5.v, 2.v, 1.v` part from `sv.add./m=r3 5.v, 2.v, 1.v` to RT, RA, RB19:27
ghostmansdAt openpower-isa/src/openpower/decoder/, `opregfields = zip(fields, v30b_regs)  # err that was easy`...19:29
ghostmansdThe comment states that was easy, but, considering how fields are constructed above, that was _not_ :-D19:29
lkclok 1 sec let me bring up the python stuff..19:33
ghostmansdThat's the line I've been talking about19:35
ghostmansdA lot precedes this "that was easy"19:35
lkclyes. sorry, was just looking to see if there's an option in gitweb to shorten URLs19:37
ghostmansdAt our svp64 branch in binutils (git://, we already have opcodes/ppc-svp64-opc.c which contains SVP64 records19:37
lkclso the first thing to note is, the format for EXTRA2 and the format for EXTRA3 is slightly different.19:38
lkclEXTRA2 is 2-bits, one of them is "is this scalar, or is it vector"19:38
lkclso when "scalar", the reg number (0-127) is split up:19:40
lkclbits[0..4] ==> directly into the 32-bit field RT/RA/RB19:40
lkclbit 5 ==> directly into the SECOND bit of EXTRA219:40
lkclnotice that that's only 6 bits? and that the reg numbers are supposed to be 7?19:41
ghostmansdYou mean sv_etype field at binutils:opcodes/ppc-svp64-opc.c, right?19:41
lkclsend me the link so i can see it19:41
lkcl1 sec i can find it19:41
lkclyes, sv_etype.  that's an EXTRA3 example which is 3-bit19:43
lkclline 3171 (fdmadds) is EXTRA2 (2-bit)19:43
ghostmansdAha, OK19:44
lkclso let's stick with EXTRA2 for now19:44
ghostmansdLet's take some example, e.g. `sv.add./m=r3 5.v, 2.v, 1.v`19:44
lkclso if you have a ".s" then you take the 1st 5 bits and shove them into the v3.0 scalar19:44
ghostmansdI see we have 3 fields here, right?19:45
lkclright, that's ".v" and it's line 42 of ppc-svp64.opc.c which is an EXTRA319:45
ghostmansdWe split mnemonics by whitespace and then take everything but the first part (except of opcode)19:46
lkclso 5 == 0b000010119:46
ghostmansdThen, we get three fields19:46
lkclyep.  3 fields, they can be identified as RT, RA, and RB.19:46
ghostmansdNono, let's go before `.v` and bits19:46
lkclah ok sure19:46
ghostmansdFirst question: RT, RA and RB, where do they come from?19:46
lkclfrom the specification19:47
ghostmansdThat's out/in1/in2/in3 in;a=blob;f=opcodes/ppc-svp64-opc.c;h=89c5ae29b349453dcf5f5d2655ec672ec0067642;hb=refs/heads/svp64#l55?19:47
ghostmansdAha, OK, now it becomes clearer19:47
lkcltake a look at this:
ghostmansdSo we basically clean the string, split by whitespaces, drop colons, then map to out/inX fields?19:48
lkclthat's microwatt's decoder and it's where the names in1, in2, in3 and out come from19:48
lkcli then turned decode1.vhdl into CSV files, and kept the names (as CSV column names)19:49
ghostmansdOK, so out/in1/in2/in3 fields mapped to chunks in the input19:50
lkclnow, the tricky bit is: the SVP64 prefix alone is *not* enough information to determine the SVP64 field encoding19:50
ghostmansdWhat happens at;a=blob;f=src/openpower/sv/trans/;h=65aa1768fc2cff1a615bbd27c33babdb1a96099b;hb=de70844521d6b6e88e380c729f8384971803454d#l355?19:50
lkcli had to spend about a week "classifying" every single one of the instructions19:50
lkclforget that for now. it was an experiment in breaking the rules, and it caused every single nightmare i had set the rules to avoid happening :)19:51
lkcli need to rip out ldst_shift.19:52
lkclback to the "classifying".  this is what does.  basically i grouped everything by "register profile"19:52
lkclbecause there are only... what... 9 bits (i think) in the EXTRA field, but some instructions have 4 registers, some have 3, some 2, and some only 119:53
lkclso if you want to put a separate SVP64 "register extension" on all 4 registers of e.g. fmadds RT, RA, RC, RB, you have only 2 bits per register19:54
lkclhence, EXTRA2.19:54
lkclif you have add RT, RA, RB, then that's 3 registers (in1, in2, out)19:54
lkcland you can do 3 bits each19:54
lkclhence, EXTRA319:54
lkclhow do you know which 3 bits of the EXTRA field map to RT, RA, RB, or CR0, or CR1, or whatever?19:55
lkclthat's where the "SVEXTRA_IDX0/1/2/3" comes in19:55
lkclsee how that works?19:55
lkclback to the add example19:56
lkcl"add RT, RA, RB" which starts at line 3219:56
lkclRA is marked as "in1" but then look at line 43, it says "in1 is in SVEXTRA_IDX1"19:57
lkcltherefore, the 3-bit EXTRA3 information associated with RA goes into EXTRA[3..5]19:57
lkclRB is marked as "in2" at line 35, but then look at line 44, it says "in2 is SV_EXTRA_IDX2"19:58
lkcltherefore, the 3-bit EXTRA3 information associated with RB goes into EXTRA[6..8]19:58
programmerjakelkcl, i can buy the arty today, can you double-check the email i sent?19:58
ghostmansdlkcl, makes sense20:00
lkclRT is marked as "out" (line 37), and at line 46, out is marked "SVEXTRA_IDX0"20:00
lkcltherefore, the 3-bit EXTRA information for RT goes into EXTRA[0..2]20:00
lkclprogrammerjake, replied.20:00
lkclBUT, we're still not done! :)20:00
ghostmansdlkcl, the idx/field processing...20:01
ghostmansdis it here?;a=blob;f=src/openpower/sv/trans/;h=65aa1768fc2cff1a615bbd27c33babdb1a96099b;hb=de70844521d6b6e88e380c729f8384971803454d#l42820:01
lkclnotice that at line 40, cr_out is marked as "CR0"20:01
lkcl1 sec... :)20:01
programmerjakealso, hi ghostmansd!20:01
ghostmansdhi programmerjake!20:01
ghostmansdlong time no see :-)20:01
lkcland CR0, at line 49, is *also* marked as "SVEXTRA_IDX0".  but, for encode purposes, you only need to fill in the EXTRA[0..8] bits once20:02
lkclright, yes, idx/field processing: yes it is20:02
programmerjakewelcome back!20:03
lkcllines 428-447 are basically the process i just described, the taking of "SVP64_xxxSEL_XX" and combining it with "SVP64_SVEXTRA_IDXyyy"20:04
lkclso you do this:20:04
lkcl* take the instruction "add. 5.v, 2.v, 1.v" and identify that RT=5.v, RA=2.v and RB=1.v20:05
lkcl* for RT, look up both out and out2 and see if they are "OUTSEL_RT"20:05
lkcl* if so, then look up the corresponding sv_out (or sv_out2) and find the SVP64_SVEXTRA_xxxx index20:06
lkclnow you have the offset where the split 5-bit and 2/3-bit EXTRA must go.20:07
lkclfor EXTRA3, you have *FOUR* locations20:07
programmerjakelkcl, added it to the bug report, should i buy them now or was there something else you wanted to do first?20:07
lkclIDX0 ==> EXTRA[0..1]20:07
lkclIDX1 ==> EXTRA[2..3]20:07
lkclIDX2 ==> EXTRA[4..5]20:07
lkclIDX3 ==> EXTRA[6..7]20:07
lkcland you ignore EXTRA[8] entirely20:08
lkclsorry, that was EXTRA220:08
lkclfor EXTRA3 you have *three* locations:20:08
lkclIDX0 ==> EXTRA[0..2]20:08
lkclIDX1 ==> EXTRA[3..5]20:08
lkclIDX2 ==> EXTRA[6..8]20:08
lkclprogrammerjake, no should be good.20:09
ghostmansdlkcl, thank you so much! have to check the code more and think about how it works a bit more20:10
ghostmansdat least now I have an idea where to start from20:10
lkclwhere get_extra_gpr() fits in is: there are two different encodings, scalar and vector20:10
lkclscalar is split, in python, as:20:10
lkcl5bitfield, extra = regnum[0..5], regnum[5:]20:11
lkcland vector is split, in python, as:20:11
lkclextra, 5bitfield = regnum[0:2], regnum[2:]20:12
lkclbut, butbutbut20:12
lkclfor EXTRA2 you have to *truncate* (throw away) some of those bits!20:12
lkclbecause you only have 1 bit available!20:13
lkclone bit of EXTRA2 is "scalar/vector" bit, and that leaves only 1 spare bit20:13
lkclfor EXTRA3 there is still 1 bit for "scalar/vector" but there are *two* bits for storing the "extra" regnum-extension-info20:13
lkclthat's where these asserts come in:20:14
lkclfor EXTRA2, the scalar range is only 0..63 because there's only 1 bit20:15
lkcland the vector range is r0 r2 r4 r6 .... r12620:15
lkcl(the comment is wrong, it's increments of 2 not 4)20:15
lkclbasically the entire thing is a massive bodge :)20:20
lkclmeeting 7min21:53
lkcltoshywoshy, cesar lxo programmerjake markos ^21:53

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