| excited-mango[m] | Hi | 00:02 |
|---|---|---|
| programmerjake | hi | 00:15 |
| purple-mango | Hi! | 02:00 |
| programmerjake | hi | 02:00 |
| ghostmansd | lkcl, speaking of copy&paste | 10:25 |
| ghostmansd | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/trans/svp64.py#l1098 | 10:25 |
| ghostmansd | I suggest to make the stuff recursive | 10:25 |
| ghostmansd | because, frankly, we had a series of commits and this just gets dirtier | 10:26 |
| ghostmansd | or, well, rather not recursive, but at least wrap it in routine which takes insn and fields | 10:27 |
| ghostmansd | but rather recursive, that is, reconstruct the insn after emitting the prefix and then call translate_one again | 10:28 |
| ghostmansd | also, this bit: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/trans/svp64.py#l267 | 10:30 |
| ghostmansd | is outdated as well, or, rather, is copy & paste error; cf. remap here: https://libre-soc.org/openpower/sv/remap/ | 10:31 |
| ghostmansd | so, lkcl, if you don't object, I'll refactor this stuff a bit, OK? | 10:38 |
| ghostmansd | but binutils first | 10:38 |
| lkcl | ghostmansd, be very very careful and make absolutely sure it matches with fields.txt | 10:41 |
| lkcl | bear in mind that the unit tests actually work | 10:42 |
| lkcl | it took me about an hour to realise yesterday that the ordering "fields[n] << 31-NN" is perfectly fine on e.g. setvl | 10:42 |
| lkcl | and it was just the comments | 10:42 |
| lkcl | right. | 10:43 |
| lkcl | that page - https://libre-soc.org/openpower/sv/remap/ - is for the *SPRs* | 10:44 |
| lkcl | it is *NOT* for the instruction format | 10:44 |
| lkcl | the arguments to the svremap instruction do **NOT** repeat **NOT** have anything to do with the ordering of the fields that the svremap instruction places those arguments into the Special Purpose Register named REMAP | 10:45 |
| lkcl | here is the link between the two: | 10:46 |
| lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/simplev.mdwn;h=8a21f038075e94668fcb344cff1260db8cc1162b;hb=HEAD#l64 | 10:46 |
| ghostmansd | fields.txt has the same | 10:46 |
| lkcl | let me take a look | 10:46 |
| ghostmansd | even if it hadn't... | 10:46 |
| programmerjake | lkcl, if you don't have a sufficient dose of maps from sv remap, you can get some more from xkcd maps: https://xkcd.com/2617/ | 10:46 |
| lkcl | SVRM form | 10:46 |
| ghostmansd | well, two mo1 args seem to be an error anyway :-) | 10:47 |
| ghostmansd | |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 | | 10:47 |
| ghostmansd | | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO | / | | 10:47 |
| lkcl | ghostmansd, yes, comment cut/paste | 10:47 |
| lkcl | i know the unit tests work so am not expecting there to be any changes | 10:47 |
| lkcl | programmerjake, cool, that has to go on the page :) | 10:47 |
| lkcl | although i am reminded of people trying to drive through fields to get onto a motorway due to errors... | 10:48 |
| programmerjake | all i can think of are the probably-untrue stories I've heard of driving off cliffs because google maps thought that was a road | 10:49 |
| programmerjake | or into lakes or similar | 10:49 |
| lkcl | i mean it's common sense that if the satnav says "drive for 500 miles into the middle of death valley" that you should maybe think about that? | 10:50 |
| lkcl | ghostmansd, updated | 10:50 |
| lkcl | 267 insn |= fields[6] << (31-21) # pst , bit 21 | 10:50 |
| programmerjake | well...i've driven through death valley before... | 10:51 |
| lkcl | cool! | 10:51 |
| programmerjake | more specifically my parents were driving and i was probably reading a book...that was like 15yr ago | 10:51 |
| programmerjake | lkcl, was wondering what you thought of moving obviously unused .py files in ieee754fpu into an unused folder like in soc...e.g. files that have an import error? | 10:55 |
| ghostmansd | lkcl, thumbs up! | 10:55 |
| lkcl | ghostmansd, also added cut/paste the NNN-Form so that linking the fields to the bits is easier | 10:55 |
| lkcl | yes really everything there in svp64.py to construct these instructions should be auto-generated from using DecodeFields | 10:57 |
| lkcl | but it's like... mmm.... there's not that many of them, you know? | 10:57 |
| lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=e4142b9e970ae21639ed5a8884d193f57ffc463a | 10:57 |
| programmerjake | every new bitmanip/bigint instruction we add has to go in svp64.py, since binutils doesn't support them and we'd rather not write our test programs in binary | 10:59 |
| programmerjake | doesn't support them yet* | 10:59 |
| ghostmansd | fuck, binutils do indeed stick to 256 operands | 11:05 |
| ghostmansd | int fx_pcrel_adjust : 8; | 11:05 |
| ghostmansd | the operand index is then being re-used, unfortunately | 11:05 |
| ghostmansd | luckily they had an assert which checks operand size and I hit it and saw the comment | 11:06 |
| purple-mango | Hey, I'm very interested in developing with Libre-SoC. I love the objective of creating truly secure and transparent hardware so ordinary people can truly trust their computers. I have a bunch of ideas about achieving that objective. I have a bunch of time on my hands, so I'd like to learn more about contributing | 11:07 |
| programmerjake | ghostmansd: reminds me of the nightmare of trying to get llvm to compile ir generated by my program, if the ir is incorrect then llvm just behaves weirdly/crashes unless you happen to have a debug build, where it asserts | 11:09 |
| programmerjake | purple-mango: welcome! | 11:10 |
| ghostmansd | programmerjake, yeah, one of the moments you know that many asserts are not that bad | 11:11 |
| lkcl | purple-mango, cool! | 11:12 |
| ghostmansd | had they written the code differently, by the way, they could even raise this crap statically | 11:13 |
| programmerjake | since it's 3am here, i'm going to go to sleep. gn all! | 11:13 |
| lkcl | programmerjake, ok :) | 11:13 |
| ghostmansd | programmerjake, good night! | 11:14 |
| lkcl | purple-mango, love to hear more. the general idea is to do as much automated as possible, apply software engineering techniques to hardware | 11:14 |
| lkcl | compilers, code-generators, machine-readable file-formats, etc | 11:14 |
| lkcl | we're funded by NLnet and NGI POINTER: are you European or based in Europe by any chance? | 11:15 |
| programmerjake | lkcl, can you post your response to my question about moving unused files in ieee754fpu on the mailing list? thx! | 11:15 |
| lkcl | programmerjake, when i see it yes! | 11:15 |
| programmerjake | https://libre-soc.org/irclog/%23libre-soc.2022-05-10.log.html#t2022-05-10T10:55:07 | 11:16 |
| purple-mango | I also have some questions to start. How come Libre-SoC uses power instead of RISC-V? And does the crypto router asic include an open source ethernet PHY? And is there any disadvantage to using the matrix brdige to connect to this IRC channel? | 11:16 |
| purple-mango | Also I'm in the US | 11:17 |
| ghostmansd | int opindex = fixP->fx_pcrel_adjust & 0xff; | 11:17 |
| lkcl | programmerjake, got it willdo | 11:17 |
| ghostmansd | any idea why they do it if they have `int fx_pcrel_adjust : 8;`? | 11:17 |
| ghostmansd | I mean, what's the point of masking it for the first place? | 11:18 |
| lkcl | purple-mango, that's a long story, about RISC-V | 11:18 |
| lkcl | ghostmansd, sigh, probably legacy or just... because? | 11:18 |
| programmerjake | lkcl: thx! | 11:18 |
| lkcl | the cryptorouter will use opencores ethmac unless we find something better | 11:18 |
| programmerjake | gn | 11:18 |
| purple-mango | And the idea of applying software engineering techniques to hardware design is really fascinating to me | 11:19 |
| ghostmansd | this crap drives me crazy, I cannot even re-use their fine machinery because they covered it with artificial limitations | 11:19 |
| purple-mango | programmerjake, gn | 11:19 |
| lkcl | https://github.com/xfguo/ethmac | 11:19 |
| lkcl | and if you use the matrix bridge at least you get a continuous presence. i achieve it by simply leaving my laptop on 100% | 11:20 |
| lkcl | not the best method :) | 11:20 |
| lkcl | the best *technical* answer as to why we're not using RISC-V is here: https://news.ycombinator.com/item?id=24459314 | 11:21 |
| purple-mango | If the crypto router asic is using ethmac, would it need to interface with a proprietary external ethernet PHY, or does ethmac include both the MAC and the PHY layer? | 11:22 |
| lkcl | for me as a software engineer it's blindingly-obvious that you use a standard programming language known by 1/3 of the world's programmers to perform for-loops and use recursion in a *good* language to create HDL | 11:22 |
| lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_decoder.py;hb=HEAD | 11:22 |
| lkcl | PHYs are Mixed Analog-Digital | 11:23 |
| lkcl | it would be insane to try to tackle that. | 11:23 |
| lkcl | requiring an additional 12 months and a minimum additional funding USD 250,000 | 11:23 |
| lkcl | just to try to create a mixed Analog-Digital ethernet PHY. | 11:23 |
| lkcl | there's only so much we can tackle at once, here | 11:24 |
| lkcl | power_decoder.py reads machine-readable files from two locations: | 11:24 |
| lkcl | 1) CSV files containing the instruction fields | 11:25 |
| lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=openpower/isatables;hb=HEAD | 11:25 |
| lkcl | 2) Power ISA "Forms" containing field members and their bit-positions | 11:25 |
| lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isatables/fields.text;hb=HEAD | 11:25 |
| excited-mango[m] | lkcl: Why would it cost so much money? | 11:27 |
| purple-mango | Also I'm just gonna use matrix as excited-mango. I like the client-side persistence | 11:27 |
| lkcl | excited-mango[m], 130 nm MPW Shuttle runs are USD 50,000 | 11:29 |
| lkcl | although now you can use ChipIgnite from efabless that's down to "only" USD 8,000 | 11:29 |
| lkcl | typical engineers with mixed Analog-Digital are USD 125 per hour *and worth it* | 11:29 |
| lkcl | and you can appreciate that 5-6 months of "engineering" time is not unreasonable. | 11:30 |
| lkcl | 5-6 months is 1,200 hours appx | 11:30 |
| lkcl | 1,200 times USD 125/hr is USD 150,000 just in engineering time | 11:30 |
| lkcl | then they will, if they are a Contractor, need to license proprietary tools including a decent SPICE Simulator | 11:31 |
| lkcl | for individuals, Cadence (etc.) is USD 100,000 | 11:31 |
| lkcl | most discussions in VLSI involve amounts where they drop three zeros off the front, routinely, as an industry-standard practice for communication and discussion. | 11:32 |
| lkcl | which is quite a hilarious contrast to Open Source FPGA developers discussing buying $100 FPGA boards. | 11:33 |
| excited-mango[m] | Okay that's a fair point. On the other hand, doesn't using a proprietary PHY undermine the security through transparency provided by the crypto router asic? | 11:34 |
| excited-mango[m] | Because you still have a blackbox device in your network stack | 11:34 |
| lkcl | we can't do everything | 11:34 |
| lkcl | one thing at a time | 11:34 |
| lkcl | at least, it's reasonable to assume that not every PHY in the world has been compromised | 11:35 |
| lkcl | but we cannot tie our efforts down to "there's no Libre/Open PHY therefore we should not even bother" | 11:36 |
| lkcl | that way, nobody will ever begin because nobody ever begun | 11:36 |
| lkcl | creating mixed Analog-Digital ASICs is extremely hard | 11:37 |
| excited-mango[m] | Ah makes sense. What if it was FPGA based instead of ASIC based? | 11:37 |
| lkcl | the variable-voltages and non-uniform frequencies of the Analog side hit the Digital side very hard | 11:37 |
| lkcl | do you mean, an FPGA that contains a built-in Ethernet PHY? | 11:37 |
| lkcl | or do you mean, "what if the crypto-router design was FPGA-based?" (it is anyway, we have to, in order to test it) | 11:38 |
| excited-mango[m] | Nah, I mean a FPGA with a libre, soft-core ethernet PHY, that would interface with the crypto router asic that runs something like ethmac | 11:40 |
| lkcl | yes, that's a step we have to do along the way | 11:40 |
| lkcl | otherwise there's no point doing an ASIC, if the design is not FPGA-proven | 11:41 |
| lkcl | or, you can, but it's hellishly risky | 11:41 |
| lkcl | i'm currently fighting nextpnr-xilinx to get it to work with the Arty-A7-100t | 11:41 |
| excited-mango[m] | I found a bunch of projects on GitHub that involve a softcore phy. They all have their limitations, but their existence makes me think a general-purpose, soft core ethernet PHY is an attainable goal: | 11:49 |
| excited-mango[m] | https://github.com/enjoy-digital/liteeth/tree/master/liteeth/phy | 11:49 |
| excited-mango[m] | https://github.com/alexforencich/verilog-ethernet | 11:49 |
| excited-mango[m] | https://github.com/corundum/corundum (datacenter-speed ethernet MAC using the verilog-ethernet PHY) | 11:49 |
| excited-mango[m] | <lkcl> "or, you can, but it's hellishly..." <- Yah that makes sense | 11:49 |
| lkcl | the litex core developer has been so rude and so unethcial that we're not going to use it. and the development style and practices in litex are problematic for technical and maintenance reasons | 11:51 |
| lkcl | (wildcard imports, deep cascading OO multiple inheritance with use of identical class names *on top* of wildcard imports) | 11:51 |
| lkcl | alex forencich's work uses AXI4-Streams and would need conversion to Wishbone | 11:52 |
| excited-mango[m] | What do you mean unethical? | 11:52 |
| excited-mango[m] | lkcl: Yikes | 11:52 |
| lkcl | plus, further investigation shows that its internal design is hard-tied to Xilinx FPGAs | 11:52 |
| lkcl | and critically relies on the Xilinx "DMA" Block which is a hard-macro provided by Xilinx FPGAs | 11:53 |
| lkcl | consequently for an ASIC we would have to implement our own DMA Engine | 11:53 |
| lkcl | definition of an ethical act: "to increase truth, awareness, love, or creativity, for one or more people (including yourself), *without* decreasing *any* of those same four underlying qualities for anyone" | 11:54 |
| lkcl | in simple terms: ethical means "always do good, never do harm" | 11:54 |
| lkcl | therefore, operating unethically inherently, put simply, "they did harm" | 11:55 |
| lkcl | the project's been running for just over 4 years, now: we've had to put up with a lot of crap | 11:56 |
| * lkcl phone call brb | 11:56 | |
| excited-mango[m] | I meant what unethical stuff did the person do, not what does unethical mean? | 11:58 |
| lkcl | excited-mango[m], because they monitor these channels, and then use any discussion to continue to do damage to my reputation, i'd very much prefer not to discuss it | 12:05 |
| excited-mango[m] | lkcl: Oh yikes. We don't have to talk about it | 12:06 |
| excited-mango[m] | Also, I may be wrong, but I think we're both looking at the Ethernet PHY from a different perspective. It seems like you're aiming for it to be an ASIC. And while I'd also like for it to be an ASIC, I feel like that's out if my skill level for a little while, so I'd be fine developing and sticking with a 1Gb/s FPGA based Ethernet PHY until I feel I have enough of a grasp on ASICs. Do you have any specific reasons for avoiding | 12:06 |
| excited-mango[m] | putting FPGAs into the product that uses the crypto router asic? | 12:06 |
| lkcl | aiming for an ASIC, but we *have* to do an FPGA version along the way | 12:09 |
| lkcl | that's absolutely critical | 12:10 |
| lkcl | consquently i have a Digilent Arty-A7-100t | 12:10 |
| lkcl | and it happens to have a 10/100 Eth PHY on it that would be exactly compatible with the opencores eth_mac HDL | 12:10 |
| excited-mango[m] | Yeah that makes sense | 12:11 |
| excited-mango[m] | Btw there's been significant progress on getting the XC7K{325T/420T/480T}s working with project xray over the last 3 weeks | 12:13 |
| lkcl | niice | 12:21 |
| lkcl | all it takes is someone to properly fund the provision of the boards containing those FPGAs, and their engineering time | 12:24 |
| excited-mango[m] | There's already a $100 XC7K325T SoM by QMTech on Aliexpress | 12:25 |
| ghostmansd | of course this damned `int fx_pcrel_adjust : 8` is in common code, f*ck | 13:46 |
| ghostmansd | I see no other option but duplicate chunks of code, sorry, this stuff is not a candidate for the code re-use | 13:47 |
| ghostmansd | This likely leads to the fact that I have to parse this in a different way | 13:50 |
| ghostmansd | lkcl, I've just realized I have no idea how to create the account on bugzilla :-) | 14:01 |
| ghostmansd | hm, also, it looks like port 922 doesn't work on my side at git.libre-soc.org | 14:22 |
| ghostmansd | https://pastebin.com/chAA8F1S | 14:23 |
| ghostmansd | At the same time, 80 and 443 ports work | 14:23 |
| lkcl | ghostmansd, doh :) | 14:31 |
| lkcl | ghostmansd, you *must not* attempt to connect via a standard username | 14:33 |
| lkcl | the *only* username permitted is: gitolite3 | 14:33 |
| ghostmansd | `ssh -v -p922 gitolite3@46.235.227.77` | 14:33 |
| ghostmansd | doh | 14:33 |
| ghostmansd | `ssh -v -p922 gitolite3@46.235.227.77` | 14:34 |
| ghostmansd | `ssh -v -p922 gitolite3@git.libre-soc.org` | 14:34 |
| ghostmansd | that's what I try to do | 14:34 |
| lkcl | attempts to use anything other than gitolite3 will result in an instant fail2ban cutoff | 14:34 |
| lkcl | you attempted a login with an unauthorised username at 14:18 and your IP address is now blacklisted. | 14:35 |
| lkcl | i will search for it and clear it. | 14:35 |
| ghostmansd | hm... could that be a legacy 3mdeb account? | 14:35 |
| ghostmansd | thank you! | 14:36 |
| lkcl | no, it's that you didn't follow the instructions | 14:37 |
| lkcl | you attempted "ssh ghostmansd@git.libre-soc.org" | 14:37 |
| lkcl | or | 14:37 |
| lkcl | from a local login named ghostmansd | 14:37 |
| lkcl | attempted just "ssh git.libre-soc.org" | 14:37 |
| lkcl | or | 14:37 |
| ghostmansd | hm, perhaps that could happen when I checked why git clone doesn't work | 14:38 |
| lkcl | in ~/.ssh/config you have an override setting which... | 14:38 |
| lkcl | yes almost certainly | 14:38 |
| lkcl | i've removed the fail2ban ban, now | 14:38 |
| ghostmansd | yeah it works now | 14:39 |
| lkcl | excelllent | 14:39 |
| ghostmansd | thank you Luke! | 14:39 |
| ghostmansd | sorry to bother :-( | 14:39 |
| lkcl | no problem | 14:39 |
| lkcl | internet access is flakey as hell at the moment | 14:39 |
| ghostmansd | I'm in the middle of switching the accounts and SSH keys, that's why I might have some issues | 14:40 |
| ghostmansd | I recalled that other old laptop still has the old SSH key, not "ghostmansd" one | 14:40 |
| ghostmansd | ...aaaaaand here the troubles started | 14:40 |
| ghostmansd | when you have the time, could you, please, also help me with creating a "ghostmansd" user at bugzilla? | 14:41 |
| ghostmansd | or, rather, switching the old one | 14:41 |
| ghostmansd | (if this is possible at all) | 14:41 |
| lkcl | ghostmansd, you can just update the email address in the settings. | 14:43 |
| lkcl | no need for me to get involved in doing that, it's standard bugzilla account user-management | 14:44 |
| lkcl | unless you get really stuck | 14:44 |
| ghostmansd[m] | lkcl, thanks for tip, it worked! | 15:15 |
| lkcl | awesome | 15:16 |
| ghostmansd[m] | Cool, I didn't know it has option to change email | 15:17 |
| ghostmansd[m] | But, frankly, I don't even remember how I got this account :-D | 15:17 |
| openpowerbot | [mattermost] <lkcl> ghostmansd[m], i created it because spammers started creating random accounts and random bugreports | 15:49 |
| openpowerbot | [mattermost] <lkcl> so i had to disable account-creation and do it manually. sigh | 15:50 |
| octavius | Is the chat in 10 min? | 21:52 |
| programmerjake | meeting in 8min | 21:52 |
| octavius | Thanks programmerjake | 21:53 |
| lkcl | excited-mango[m], we have a weekly social meeting every tuesday, starts in 5m if you're interested. on jitsi | 21:56 |
| lkcl | non-restricted URL, so we don't publish it, programmerjake can you PM excited-mango[m] with it? | 21:57 |
| programmerjake | sent | 22:06 |
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