| lkcl | Veera[m], please update the TOML fields for 883 (etc.) | 05:13 |
|---|---|---|
| programmerjake | so does that mean you're opening the fix-cvc5 bug report? or should I | 05:17 |
| lkcl | you do it please, it's 5:22am here | 05:22 |
| lkcl | i'll do budgets later (there's EUR 1600 available, all yours, just thinking how to do it) | 05:23 |
| programmerjake | k | 05:24 |
| programmerjake | lkcl, pushed cvc5.git, you can make the repo public now... | 05:42 |
| Manili | Hello everyone. I have some questions. First of all I am wondering to know how are you going to do the physical design phase of a below 130nm chip? Because AFAIK there is no open-source PDK out there for such nodes, yet. | 09:03 |
| Manili | Second, What are differences between Coriolis and OpenLane? What leads you to use Coriolis over OpenLane or the open-source tools? | 09:05 |
| programmerjake | iirc one of the differences is coriolis supports timing-driven layout -- needed for high clock frequencies, openlane doesn't support that yet last I checked | 09:07 |
| programmerjake | lkcl would likely know more details, he'll probably be awake in around 2hr | 09:09 |
| Manili | Thanks a lot Jacob. | 09:11 |
| programmerjake | iirc for lower than 130nm we are planning on using the proprietary design tools simply because we have no other choice without taking years and millions of dollars to develop them ourselves. | 09:12 |
| Manili | So the results would not be published publicly, right? | 09:14 |
| programmerjake | everything we reasonably can publish will be public | 09:15 |
| programmerjake | if it includes NDAed stuff from a foundary, that can't be published, but we might be able to publish outlines or low-level block diagrams or something...the original nmigen source should be completely public | 09:17 |
| Manili | About the tools, AFAIK OpenLane managed to do the PD on 7nm tech-node design. I don't know about the details but it worth it to do some research about it. | 09:18 |
| programmerjake | neat! | 09:19 |
| Manili | Check this out: https://github.com/The-OpenROAD-Project/asap7 | 09:20 |
| Manili | I'm not sure whether it can help or not... But better than nothing! | 09:20 |
| programmerjake | ooh, didn't know about that... | 09:24 |
| programmerjake | shared it on the mailing list: https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-July/005068.html | 09:33 |
| programmerjake | thx Manili! | 09:35 |
| Manili | You're very welcome. So happy to help. | 09:45 |
| Manili | Sorry guys for asking too much questions. If I'm not wrong you are using "Raptor CS", "fed4fire" and local FPGAs for emulation, right? are there any cloud-based FPGA implementation, yet? I mean something like Firesim from UCB. | 10:14 |
| lkcl | Manili, https://www.raptorcs.com/ are a sponsor | 11:24 |
| lkcl | https://www.fed4fire.eu/ provided access to large clusters of computing at universities world-wide | 11:25 |
| lkcl | https://libre-soc.org/HDL_workflow/ECP5_FPGA/ is one of the FPGAs | 11:26 |
| lkcl | https://libre-soc.org/HDL_workflow/nextpnr-xilinx/ gets you up-and-running with a Digilent Arty a7-100t | 11:26 |
| lkcl | Veera[m], thx, everything's moved to "submitted but not yet paid" in budget-sync | 11:35 |
| Manili | Are the FPGAs' resources enough to emulate all libreSOC? | 11:40 |
| lkcl | Manili, at the moment yes | 11:41 |
| lkcl | single-core, scalar, integer-only, 64-bit, L1 I/D-Cache, RADIX MMU | 11:42 |
| lkcl | by the time we get to multi-core SMP, FP, SVP64 and OoO, absolutely no chance | 11:43 |
| lkcl | this is standard fare for FPGAs. | 11:43 |
| Manili | Do you have any plans for bigger designs? Or just left it for the future? | 11:44 |
| lkcl | of course. that's always been the goal. yes. | 11:46 |
| lkcl | answering your first question: that's what RED Semiconductor Ltd is for. | 11:46 |
| lkcl | coriolis2 was far more mature and stable than openlane. openlane had not been announced when we started | 11:47 |
| lkcl | and it is still a much more mature and stable RTL2GDS system | 11:48 |
| lkcl | Jean-Paul knows what he's doing, and when he says "there will be problems XYZ occurring if targetting 130nm" i can trust that he knows what he's talking about | 11:49 |
| lkcl | 180nm is by far the most commonly-used geometry *in the world*, it is also the cheapest, and it is "bullet-proof" | 11:49 |
| lkcl | by the time you get to 130nm you get: | 11:50 |
| lkcl | * EMI radiation effects between wires (cross-talk) | 11:50 |
| lkcl | * impedance (RC) problems on track driving, proportional to the *length* of the wire | 11:50 |
| lkcl | and many many more issues, all of which have to be directly taken into account by the layout software | 11:51 |
| lkcl | there's a 2nd NLnet Grant which i got in for LIP6 on their behalf, to help put the pieces in place to take on the smaller geometries | 11:52 |
| lkcl | https://bugs.libre-soc.org/show_bug.cgi?id=748 | 11:52 |
| Manili | How do you access TSMC 180nm PDK? Are you doing the design based on non-NDA info and then RSC change them to TSMC specific layout? | 11:56 |
| Manili | RSC => RED Semicon LTD | 11:57 |
| lkcl | ok, so RED Semiconductor Ltd will be a one-way door on commercialisation, keeping to its public committment of full transparency | 11:59 |
| lkcl | and because i am the CTO it will *not* be doing "spongeing and exploitation of FOSSHW" | 11:59 |
| lkcl | RED Semiconductor Ltd will sign the NDAs and agreements or use whatever subcontractors are required to reach its commercialisation goals | 12:00 |
| lkcl | because Libre-SOC is a FOSSHW project and has absolutely no way to realistically achieve any commercial goals of any kind, short of being donated 10+ billion dollars and going shopping for a Foundry | 12:01 |
| lkcl | the way it worked for ls180: | 12:02 |
| lkcl | Jean-Paul Chaput, through Sorbonne University, already had an Academic NDA Agreement in place with Imec and TSMC | 12:02 |
| lkcl | i therefore used FreePDK45 to create "in-parallel" GDS-II files (which, like ASAP7, have absolutely no chance whatsoever of ever being put into silicon) | 12:03 |
| lkcl | and Jean-Paul then took the coriolis2 python layout scripts and adapted them to TSMC's NDA'd 180nm PDK. | 12:04 |
| lkcl | *at no time* did i, as a member of the Libre-SOC FOSSHW team, sign a TSMC NDA, violate a TSMC NDA, get access to a TSMC NDA, get access to a TSMC PDK in violation of a TSMC NDA | 12:05 |
| lkcl | so our funding remit, of full transparency, from NLnet, is still intact. | 12:05 |
| lkcl | we had a lot of misunderstandings on that one, on the internet, in past discussions (reddit, ycombinator etc.) | 12:07 |
| lkcl | people believed i *had* to have signed a TSMC NDA in order to achieve the ls180 tape-out. it was in fact done entirely by LIP6 (Sorbonne University) | 12:08 |
| lkcl | something similar (ish) will happen when RED Semiconductor gets funded. | 12:09 |
| lkcl | https://git.libre-soc.org/?p=soclayout.git;a=tree;f=experiments9;h=074fa82e57c1185c5c21785d4c4456fa7e224ae1;hb=81d267598a931153815db6cbf0e44f86973575aa | 12:11 |
| lkcl | see the 2 subdirectories, there | 12:11 |
| lkcl | drwxr-xr-x-freepdk_c4m45tree | history | 12:11 |
| lkcl | drwxr-xr-x-tsmc_c018tree | history | 12:11 |
| Manili | So as you mentioned there is no difference b/w FreePDK45 and ASAP7 in terms of chances to be fabricated. Why didn't you choose other PDKs and leave the rest to Jean-Paul for conversion process? I mean what is the reason behind choosing FreePDK45? | 12:13 |
| Manili | FreePDK45 means it is a mock of 45nm process, right? | 12:15 |
| lkcl | ASAP7 and FreePDK45 are "academic" - hypothetical - PDKs, yes. no Foundry supports them | 12:16 |
| lkcl | because it's available | 12:16 |
| lkcl | to work entirely transparently you have to have *a* PDK | 12:17 |
| lkcl | FreePDK45 was - is - available. | 12:17 |
| lkcl | remember the ls180 project was started long before sky130 existed | 12:18 |
| lkcl | it pre-dates google's sky130 public announcement by at least 18 months. | 12:18 |
| lkcl | basically, there's a hell of a lot of history already | 12:29 |
| lkcl | (it's been almost 4 years) | 12:29 |
| lkcl | and it's a huge complex multi-faceted negotiation of requirements | 12:30 |
| Manili | OK thx lkcl. | 13:04 |
| lkcl | Manili, no problem :) | 13:07 |
| lkcl | we've got on-boarding processes in place so as not to completely overwhelm people | 13:08 |
| lkcl | what's your main areas of expertise? what can you do, and what would you *like* to do? :) | 13:08 |
| lkcl | jn: moornin. got a question for you. | 13:08 |
| jn | hi lkcl! | 13:08 |
| jn | what is it? | 13:08 |
| lkcl | the Nuvoton rev-eng you're doing, is the Card a plugin? | 13:09 |
| lkcl | into the motherboard you're working on? | 13:09 |
| lkcl | i'm looking to put together an NLnet Grant Request (for the Aug 1st deadline) | 13:09 |
| jn | no, on all the boards that i have the BMC is directly on the mainboard | 13:09 |
| lkcl | drat | 13:09 |
| lkcl | are there any that are, that you know of? | 13:09 |
| lkcl | that are very common, i mean | 13:10 |
| lkcl | even if they're older | 13:10 |
| lkcl | i need something where we can propose: | 13:10 |
| lkcl | "if you fund us we'll make a FOSSHW replacement plugin BMC board with an FPGA and/or OrangeCrab adapter and it's worth funding because there are miiiiilllions of end-users who can benefit" | 13:11 |
| jn | for wpcm450, not that i'm aware. there is a different kind of plugin cards on the dell T310 (and similar boards) though: A card with an Ethernet PHY and an SD slot, which are both used by the BMC, but the BMC is still hard-wired on the mainboard | 13:11 |
| lkcl | nnggggh drat again | 13:12 |
| jn | and another kind of BMC addon for the same mainboard that adds an eMMC flash | 13:12 |
| jn | interesting design ideas, but fundamentally different from runbmc etc. | 13:13 |
| lkcl | any other ideas? not necessarily wpcm450? | 13:13 |
| lkcl | toshywoshy mentioned that there are _some_ servers/workstations with pluggable BMCs | 13:14 |
| lkcl | ah HA! https://www.asus.com/uk/Commercial-Servers-Workstations/ASMB7IKVM/ | 13:15 |
| jn | HP had a pluggable BMC card based on an ASPEED BMC (https://www.ebay.de/itm/165492674698), but i think it was fairly rare | 13:15 |
| jn | that ASUS card is just a flash chip carrier | 13:16 |
| jn | simple to copy, but a little limited in scope | 13:16 |
| lkcl | flash chip carrier... annoying | 13:18 |
| lkcl | ok. | 13:18 |
| lkcl | i think we go for a "hypothetical" one then, instead. | 13:18 |
| lkcl | back-to-back, twin FPGAs (on separate boards) | 13:18 |
| lkcl | you'd be more than welcome to help do e.g. openbmc ports on it (as part of the NLnet Grant funded work) | 13:20 |
| lkcl | the idea would be to have one FPGA running LibreBMC / OpenBMC | 13:20 |
| lkcl | the other FPGA running microwatt / libre-soc | 13:20 |
| lkcl | and for the 1st FPGA to provide the OS and startup of the 2nd FPGA | 13:21 |
| lkcl | using IMPI, LPC, etc. etc. etc. etc. | 13:21 |
| jn | I wonder if there are mass-produced RunBMC-compatible mainboards available by now (i.e. mainboards to test against) | 13:21 |
| jn | because AFAIUI, runbmc should be suitable open standard for BMC plugin cards | 13:22 |
| lkcl | https://github.com/opencomputeproject/RunBMC | 13:23 |
| lkcl | oooOooo | 13:23 |
| jn | based on a 260-pin SODIMM connector | 13:23 |
| jn | i haven't investigated it much | 13:24 |
| jn | but some of the advantages you'd expect from an open standard, are apparent, such as having the pinout list | 13:25 |
| jn | in here https://raw.githubusercontent.com/opencomputeproject/RunBMC/master/OCP_RunBMC_Daughterboard_Card_Design_Specification_v1.4.1.pdf | 13:25 |
| jn | and the connector means no special part (just an edge connector) on the BMC card | 13:26 |
| lkcl | yyeahh that looks half decent | 13:26 |
| jn | unfortunately, my general impression with OCP has been that the designs are somewhat available, but pre-fabricated boards often aren't easy to get, because it's focused on the internal needs of big datacenter operators | 13:28 |
| jn | (IT recycling companies might have them though, sometimes) | 13:28 |
| lkcl | yehyeh makes sense | 13:28 |
| lkcl | and i think that's why the first submission wasn't accepted, because although LibreBMC is open it's still "internal needs of big datacentre operators" | 13:29 |
| lkcl | i was hoping there was something non-soldered-down in a commonly-available motherboard somewhere | 13:29 |
| * jn nods | 13:30 | |
| jn | oh wait... i just learned about OCP DC-SCM | 13:31 |
| jn | a *different* BMC card standard from OCP | 13:32 |
| jn | ... but written by Google and Microsoft instead of Dropbox | 13:32 |
| jn | and a bit newer | 13:33 |
| lkcl | yes, this is the one that Libre-BMC is doing. | 13:33 |
| jn | the DC-SCM spec is two years newer but doesn't mention runbmc | 13:33 |
| lkcl | https://opensource.googleblog.com/2022/05/DC-SCM-compatible-FPGA-based-open-source-BMC-hardware-platform.html | 13:34 |
| jn | i'm slightly disappointed in the lack of a "historical background" or "prior work" section that should mention runbmc | 13:34 |
| lkcl | Use in LibreBMC / OpenPOWER | 13:34 |
| lkcl | Open source, configurable hardware platforms based on FPGA, | 13:34 |
| lkcl | ... | 13:34 |
| lkcl | whoops | 13:35 |
| Manili | @lkcl Well to be honest I can't call my self an expert, yet. :) I have received both my BS and MS in computer architecture engineering. I had a chance to tapeout two chips under Sky130 MPW3 which was a great opportunity. I have many different favorite areas in terms of HW design but I really love to work on distributed full-chip emulation, specifically on multiple FPGAs or COTS servers, but I think it doesn't help you (at least for now). | 13:40 |
| lkcl | nice! | 13:41 |
| Manili | Well to be honest I can't call my self an expert, yet => I'm a learner and that's why I'm asking toooo many qestions :)) | 13:41 |
| lkcl | well, funny you should mention that because we have *another* NLnet Grant for cavatools | 13:41 |
| lkcl | which is a multi-core (parallel, SMP-host) ISA emulator | 13:41 |
| Manili | Really? | 13:42 |
| lkcl | yes. 1 sec | 13:42 |
| lkcl | https://mobile.twitter.com/lkcl/status/1411701772578705412 | 13:42 |
| lkcl | https://libre-soc.org/nlnet_2021_3mdeb_cavatools/ | 13:43 |
| lkcl | but also, we've got some Dual FPGA boards (Arctic Tern) arriving some time (Raptor Engineering) | 13:43 |
| lkcl | the two ECP5 FPGAs are connected back-to-back | 13:44 |
| lkcl | (via 5Gbit SERDES) | 13:44 |
| lkcl | so could be used to communicate SMP Cache-coherency as well as memory-snooping | 13:44 |
| Manili | Nice! The question is, in the future, could the full libreSOC be placed on only one FPGA (I mean only one core)? Or we need to distribute the logic itself? | 13:47 |
| Manili | Anybody working on this project? | 13:48 |
| lkcl | with an IEEE754 FP unit *and* SIMD back-end ALUs *and* out-of-order, it's extremely unlikely that an 85k LUT4 FPGA will cope | 13:48 |
| lkcl | however | 13:48 |
| lkcl | we are *very deliberately* designing flexibility / configurability in mind | 13:48 |
| lkcl | this is a python OO HDL. we have options that would be almost impossible to manage with VHDL/Verilog | 13:49 |
| lkcl | there are already.... 15 compile-time options in issuer_verilog.py | 13:49 |
| lkcl | including ones that cut back the L1 Cache sizes to fit into 45k LUT4 ECP5s | 13:50 |
| lkcl | if there are decent boards out there in the future with Libre/Open tools we'll be able to increase the capabilities that will fit | 13:51 |
| lkcl | for example i have a Digilent Nexys Video, it has an A7 *200t* (not a 100t like in the Arty A7) | 13:51 |
| lkcl | the only reason i got it is because of nextpnr-xilinx | 13:51 |
| lkcl | octavius, did you email NLnet your name/address? i did bcc you on that one, didn't i? | 13:52 |
| lkcl | new-mou-somethingsomething@nlnet.nl | 13:52 |
| Manili | No I didn't do that yet. What should I do? | 13:53 |
| octavius | No, lkcl, I'll do that now | 13:54 |
| lkcl | octavius, yes please | 13:54 |
| Manili | Oh sorry... | 13:54 |
| lkcl | Manili, the convention is to put a person's name to ping them. irc clients pick up on that and generate (annoying) attention-grabbing alerts | 13:55 |
| lkcl | i disabled *all* of them in hexchat because they piss me off :) | 13:55 |
| Manili | Well, that's hard for me to keep up with you guys. I'm from Slack planet, after all. :) | 13:56 |
| lkcl | joooy :) | 13:57 |
| octavius | lkcl: Actually I don't know which email to use? Is it the usual one we used for RFP submission? | 13:57 |
| lkcl | what's that? that's a Libre / FOSS system, right? :) | 13:57 |
| lkcl | octavius, no | 13:57 |
| lkcl | 1 sec | 13:57 |
| octavius | Manili: I joined the proj in Sep, took me a few months to get the hang of it (I still don't know most of the IRC etiquette/commands ;) ) | 13:58 |
| lkcl | octavius, fwded | 13:58 |
| octavius | thnx lkcl | 13:58 |
| lkcl | Manili, if you prefer a web client then you can register with matrix | 13:58 |
| lkcl | and they've established an automatic bridge to libera.chat | 13:58 |
| lkcl | which is why you see a lot of people with "[m]" on the end of their irc handle | 13:59 |
| Manili | octavius :D | 13:59 |
| Manili | lkcl, I'll give it a try. thx | 13:59 |
| octavius | I simply copied luke and use Hexchat, though matrix saves the message history when you're offline | 14:00 |
| markos | lkcl, speaking of the nexys, did you try it at all? | 14:00 |
| lkcl | markos, haven't had time yet! | 14:01 |
| markos | +1 hexchat | 14:01 |
| lkcl | it's not going to be hard: a single entry in nmigen-boards based on existing pinouts from other projects | 14:02 |
| lkcl | which has been done repeatedly and frequently | 14:02 |
| markos | these days I'm finishing a diy made-from-plywood 20U rack closet and when done with that, I plan to get the nexys up and running | 14:03 |
| markos | lots of cables everywhere atm | 14:03 |
| lkcl | :) | 14:04 |
| lkcl | Manili, nice board. https://www.mouser.co.uk/new/digilent/digilent-nexys-board/ 200k FPGA. | 14:04 |
| Manili | There is a company in my country which creates FPGA boards with multiple Virtex 7series on. Could be a good candidate for our goals. | 14:07 |
| Manili | BTW, Nexy is really nice. | 14:07 |
| lkcl | you mean nexys-4? | 14:08 |
| lkcl | it's only a 100t - nice as it is - and is superceded by the Arty A7 | 14:08 |
| lkcl | which has 4 PMODs | 14:09 |
| lkcl | i got *two* 1bitsquared HyperRAM PMODs which makes startup a hell of a lot easier | 14:09 |
| Manili | Is it possible to use open-source tools to program it? | 14:10 |
| lkcl | yes, i've been using nextpnr-xilinx. symbiflow also worked but it is 6x slower to route | 14:11 |
| lkcl | https://libre-soc.org/HDL_workflow/nextpnr-xilinx/ | 14:11 |
| lkcl | https://libre-soc.org/HDL_workflow/symbiflow/ | 14:11 |
| Manili | Have you ever tested SymbiFlow on 7-series? | 14:11 |
| lkcl | yes. it's... ok. | 14:13 |
| lkcl | some of the IO types are not supported (LVDS, DDR) | 14:13 |
| lkcl | where they are by nextpnr-xilinx | 14:14 |
| lkcl | but | 14:14 |
| lkcl | both are "broken" as far as adds/subs/cmps greater than 4*26-bits in length | 14:14 |
| lkcl | you have to "compensate" for that by adding "-nocarrylut" to yosys | 14:14 |
| lkcl | which results in a "punishment" of a drop in speed of 30% | 14:15 |
| lkcl | long story, look it up online. | 14:15 |
| Manili | lkcl, Great info. Thanks a lot. I'm ganna look deep into the links which you provided earlier about the multi-core ISA emulator and then I'll be right back to you. | 14:17 |
| lkcl | Manili, no problem. Peter Hsu is amazing. he was the designer of the MIPS R8000. | 14:18 |
| lkcl | ghostmansd[m], how you getting on? i'm trying to think how to get you out of a binutils bottomless pit :) | 14:37 |
| lkcl | you saw it occurred to me (at 6am sigh) that sm=1<<r3 is, realistically, never going to be suitable for macros? | 14:38 |
| lkcl | (or, sm=u3, or, sm=the-unary-r3) | 14:39 |
| ghostmansd[m] | That's OK, I almost see the light in the end of the tunnel :-) | 14:39 |
| ghostmansd[m] | Do you mean that anyone who's going to use it will anyway use it w/o macros? | 14:44 |
| ghostmansd[m] | I started implementing all predicates, I'm only not quite sure how to organize it better. | 14:50 |
| ghostmansd[m] | As for 1<<r3... https://bugs.libre-soc.org/show_bug.cgi?id=849#c27 | 14:51 |
| lkcl | ghostmansd[m], sm=^%r3 works for me. it's even shorter than sm=1<<r3 | 15:20 |
| ghostmansd[m] | Shorter for you doesn't imply shorter code in binutils :-) | 15:21 |
| ghostmansd[m] | Likely there's no such operator | 15:21 |
| ghostmansd[m] | But perhaps it's even more evident that this one is special, and at least it follows the same conventions as everything else | 15:24 |
| octavius | lkcl, it compiles :D | 16:49 |
| octavius | ....but | 16:49 |
| octavius | I had to edit the #include statements (tcl.h is now under tcl/tcl.h) | 16:49 |
| lkcl | octavius, hooraay. | 19:06 |
| lkcl | ok put that on the bugreport if you haven't already | 19:06 |
| lkcl | i'll raise the issue with jean-paul | 19:07 |
| tplaten | I have read https://github.com/Ravenslofty/yosys-cookbook/blob/master/ecp5.md it is an interesting article | 19:09 |
| lkcl | yes, some good tips on it | 19:10 |
| tplaten | currently looking at Cesar's patch from ten days ago. | 19:14 |
| lkcl | great. | 19:18 |
| tplaten | First I modify src/ecp5_crg.py to pass a flag to enable the ECLKBRIDGECS. That will be false by default | 19:35 |
| octavius | Hi lkcl, I won't be available this evening for the meeting. My uncle has arrived (he's a sailor!) so I better use the opportunity to spend time together:D | 21:11 |
| lkcl | programmerjake, meeting ^ | 22:04 |
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