Wednesday, 2022-07-13

lkclVeera[m], please update the TOML fields for 883 (etc.)05:13
programmerjakeso does that mean you're opening the fix-cvc5 bug report? or should I05:17
lkclyou do it please, it's 5:22am here05:22
lkcli'll do budgets later (there's EUR 1600 available, all yours, just thinking how to do it)05:23
programmerjakelkcl, pushed cvc5.git, you can make the repo public now...05:42
ManiliHello everyone. I have some questions. First of all I am wondering to know how are you going to do the physical design phase of a below 130nm chip? Because AFAIK there is no open-source PDK out there for such nodes, yet.09:03
ManiliSecond, What are differences between Coriolis and OpenLane? What leads you to use Coriolis over OpenLane or the open-source tools?09:05
programmerjakeiirc one of the differences is coriolis supports timing-driven layout -- needed for high clock frequencies, openlane doesn't support that yet last I checked09:07
programmerjakelkcl would likely know more details, he'll probably be awake in around 2hr09:09
ManiliThanks a lot Jacob.09:11
programmerjakeiirc for lower than 130nm we are planning on using the proprietary design tools simply because we have no other choice without taking years and millions of dollars to develop them ourselves.09:12
ManiliSo the results would not be published publicly, right?09:14
programmerjakeeverything we reasonably can publish will be public09:15
programmerjakeif it includes NDAed stuff from a foundary, that can't be published, but we might be able to publish outlines or low-level block diagrams or something...the original nmigen source should be completely public09:17
ManiliAbout the tools, AFAIK OpenLane managed to do the PD on 7nm tech-node design. I don't know about the details but it worth it to do some research about it.09:18
ManiliCheck this out:
ManiliI'm not sure whether it can help or not... But better than nothing!09:20
programmerjakeooh, didn't know about that...09:24
programmerjakeshared it on the mailing list:
programmerjakethx Manili!09:35
ManiliYou're very welcome. So happy to help.09:45
ManiliSorry guys for asking too much questions. If I'm not wrong you are using "Raptor CS", "fed4fire" and local FPGAs for emulation, right? are there any cloud-based FPGA implementation, yet? I mean something like Firesim from UCB.10:14
lkclManili, are a sponsor11:24
lkcl provided access to large clusters of computing at universities world-wide11:25
lkcl is one of the FPGAs11:26
lkcl gets you up-and-running with a Digilent Arty a7-100t11:26
lkclVeera[m], thx, everything's moved to "submitted but not yet paid" in budget-sync11:35
ManiliAre the FPGAs' resources enough to emulate all libreSOC?11:40
lkclManili, at the moment yes11:41
lkclsingle-core, scalar, integer-only, 64-bit, L1 I/D-Cache, RADIX MMU11:42
lkclby the time we get to multi-core SMP, FP, SVP64 and OoO, absolutely no chance11:43
lkclthis is standard fare for FPGAs.11:43
ManiliDo you have any plans for bigger designs? Or just left it for the future?11:44
lkclof course. that's always been the goal. yes.11:46
lkclanswering your first question: that's what RED Semiconductor Ltd is for.11:46
lkclcoriolis2 was far more mature and stable than openlane. openlane had not been announced when we started11:47
lkcland it is still a much more mature and stable RTL2GDS system11:48
lkclJean-Paul knows what he's doing, and when he says "there will be problems XYZ occurring if targetting 130nm" i can trust that he knows what he's talking about11:49
lkcl180nm is by far the most commonly-used geometry *in the world*, it is also the cheapest, and it is "bullet-proof"11:49
lkclby the time you get to 130nm you get:11:50
lkcl* EMI radiation effects between wires (cross-talk)11:50
lkcl* impedance (RC) problems on track driving, proportional to the *length* of the wire11:50
lkcland many many more issues, all of which have to be directly taken into account by the layout software11:51
lkclthere's a 2nd NLnet Grant which i got in for LIP6 on their behalf, to help put the pieces in place to take on the smaller geometries11:52
ManiliHow do you access TSMC 180nm PDK? Are you doing the design based on non-NDA info and then RSC change them to TSMC specific layout?11:56
ManiliRSC => RED Semicon LTD11:57
lkclok, so RED Semiconductor Ltd will be a one-way door on commercialisation, keeping to its public committment of full transparency11:59
lkcland because i am the CTO it will *not* be doing "spongeing and exploitation of FOSSHW"11:59
lkclRED Semiconductor Ltd will sign the NDAs and agreements or use whatever subcontractors are required to reach its commercialisation goals12:00
lkclbecause Libre-SOC is a FOSSHW project and has absolutely no way to realistically achieve any commercial goals of any kind, short of being donated 10+ billion dollars and going shopping for a Foundry12:01
lkclthe way it worked for ls180:12:02
lkclJean-Paul Chaput, through Sorbonne University, already had an Academic NDA Agreement in place with Imec and TSMC12:02
lkcli therefore used FreePDK45 to create "in-parallel" GDS-II files (which, like ASAP7, have absolutely no chance whatsoever of ever being put into silicon)12:03
lkcland Jean-Paul then took the coriolis2 python layout scripts and adapted them to TSMC's NDA'd 180nm PDK.12:04
lkcl*at no time* did i, as a member of the Libre-SOC FOSSHW team, sign a TSMC NDA, violate a TSMC NDA, get access to a TSMC NDA, get access to a TSMC PDK in violation of a TSMC NDA12:05
lkclso our funding remit, of full transparency, from NLnet, is still intact.12:05
lkclwe had a lot of misunderstandings on that one, on the internet, in past discussions (reddit, ycombinator etc.)12:07
lkclpeople believed i *had* to have signed a TSMC NDA in order to achieve the ls180 tape-out. it was in fact done entirely by LIP6 (Sorbonne University)12:08
lkclsomething similar (ish) will happen when RED Semiconductor gets funded.12:09
lkclsee the 2 subdirectories, there12:11
lkcldrwxr-xr-x-freepdk_c4m45tree | history12:11
lkcldrwxr-xr-x-tsmc_c018tree | history12:11
ManiliSo as you mentioned there is no difference b/w FreePDK45 and ASAP7 in terms of chances to be fabricated. Why didn't you choose other PDKs and leave the rest to Jean-Paul for conversion process? I mean what is the reason behind choosing FreePDK45?12:13
ManiliFreePDK45 means it is a mock of 45nm process, right?12:15
lkclASAP7 and FreePDK45 are "academic" - hypothetical - PDKs, yes.  no Foundry supports them12:16
lkclbecause it's available12:16
lkclto work entirely transparently you have to have *a* PDK12:17
lkclFreePDK45 was - is - available.12:17
lkclremember the ls180 project was started long before sky130 existed12:18
lkclit pre-dates google's sky130 public announcement by at least 18 months.12:18
lkclbasically, there's a hell of a lot of history already12:29
lkcl(it's been almost 4 years)12:29
lkcland it's a huge complex multi-faceted negotiation of requirements12:30
ManiliOK thx lkcl.13:04
lkclManili, no problem :)13:07
lkclwe've got on-boarding processes in place so as not to completely overwhelm people13:08
lkclwhat's your main areas of expertise? what can you do, and what would you *like* to do? :)13:08
lkcljn: moornin. got a question for you.13:08
jnhi lkcl!13:08
jnwhat is it?13:08
lkclthe Nuvoton rev-eng you're doing, is the Card a plugin?13:09
lkclinto the motherboard you're working on?13:09
lkcli'm looking to put together an NLnet Grant Request (for the Aug 1st deadline)13:09
jnno, on all the boards that i have the BMC is directly on the mainboard13:09
lkclare there any that are, that you know of?13:09
lkclthat are very common, i mean13:10
lkcleven if they're older13:10
lkcli need something where we can propose:13:10
lkcl"if you fund us we'll make a FOSSHW replacement plugin BMC board with an FPGA and/or OrangeCrab adapter and it's worth funding because there are miiiiilllions of end-users who can benefit"13:11
jnfor wpcm450, not that i'm aware. there is a different kind of plugin cards on the dell T310 (and similar boards) though: A card with an Ethernet PHY and an SD slot, which are both used by the BMC, but the BMC is still hard-wired on the mainboard13:11
lkclnnggggh drat again13:12
jnand another kind of BMC addon for the same mainboard that adds an eMMC flash13:12
jninteresting design ideas, but fundamentally different from runbmc etc.13:13
lkclany other ideas? not necessarily wpcm450?13:13
lkcltoshywoshy mentioned that there are _some_ servers/workstations with pluggable BMCs13:14
lkclah HA!
jnHP had a pluggable BMC card based on an ASPEED BMC (, but i think it was fairly rare13:15
jnthat ASUS card is just a flash chip carrier13:16
jnsimple to copy, but a little limited in scope13:16
lkclflash chip carrier... annoying13:18
lkcli think we go for a "hypothetical" one then, instead.13:18
lkclback-to-back, twin FPGAs (on separate boards)13:18
lkclyou'd be more than welcome to help do e.g. openbmc ports on it (as part of the NLnet Grant funded work)13:20
lkclthe idea would be to have one FPGA running LibreBMC / OpenBMC13:20
lkclthe other FPGA running microwatt / libre-soc13:20
lkcland for the 1st FPGA to provide the OS and startup of the 2nd FPGA13:21
lkclusing IMPI, LPC, etc. etc. etc. etc.13:21
jnI wonder if there are mass-produced RunBMC-compatible mainboards available by now (i.e. mainboards to test against)13:21
jnbecause AFAIUI, runbmc should be suitable open standard for BMC plugin cards13:22
jnbased on a 260-pin SODIMM connector13:23
jni haven't investigated it much13:24
jnbut some of the advantages you'd expect from an open standard, are apparent, such as having the pinout list13:25
jnin here
jnand the connector means no special part (just an edge connector) on the BMC card13:26
lkclyyeahh that looks half decent13:26
jnunfortunately, my general impression with OCP has been that the designs are somewhat available, but pre-fabricated boards often aren't easy to get, because it's focused on the internal needs of big datacenter operators13:28
jn(IT recycling companies might have them though, sometimes)13:28
lkclyehyeh makes sense13:28
lkcland i think that's why the first submission wasn't accepted, because although LibreBMC is open it's still "internal needs of big datacentre operators"13:29
lkcli was hoping there was something non-soldered-down in a commonly-available motherboard somewhere13:29
* jn nods13:30
jnoh wait... i just learned about OCP DC-SCM13:31
jna *different* BMC card standard from OCP13:32
jn... but written by Google and Microsoft instead of Dropbox13:32
jnand a bit newer13:33
lkclyes, this is the one that Libre-BMC is doing.13:33
jnthe DC-SCM spec is two years newer but doesn't mention runbmc13:33
jni'm slightly disappointed in the lack of a "historical background" or "prior work" section that should mention runbmc13:34
lkclUse in LibreBMC / OpenPOWER13:34
lkclOpen source, configurable hardware platforms based on FPGA,13:34
Manili@lkcl Well to be honest I can't call my self an expert, yet. :) I have received both my BS and MS in computer architecture engineering. I had a chance to tapeout two chips under Sky130 MPW3 which was a great opportunity. I have many different favorite areas in terms of HW design but I really love to work on distributed full-chip emulation, specifically on multiple FPGAs or COTS servers, but I think it doesn't help you (at least for now).13:40
ManiliWell to be honest I can't call my self an expert, yet => I'm a learner and that's why I'm asking toooo many qestions :))13:41
lkclwell, funny you should mention that because we have *another* NLnet Grant for cavatools13:41
lkclwhich is a multi-core (parallel, SMP-host) ISA emulator13:41
lkclyes. 1 sec13:42
lkclbut also, we've got some Dual FPGA boards (Arctic Tern) arriving some time (Raptor Engineering)13:43
lkclthe two ECP5 FPGAs are connected back-to-back13:44
lkcl(via 5Gbit SERDES)13:44
lkclso could be used to communicate SMP Cache-coherency as well as memory-snooping13:44
ManiliNice! The question is, in the future, could the full libreSOC be placed on only one FPGA (I mean only one core)? Or we need to distribute the logic itself?13:47
ManiliAnybody working on this project?13:48
lkclwith an IEEE754 FP unit *and* SIMD back-end ALUs *and* out-of-order, it's extremely unlikely that an 85k LUT4 FPGA will cope13:48
lkclwe are *very deliberately* designing flexibility / configurability in mind13:48
lkclthis is a python OO HDL. we have options that would be almost impossible to manage with VHDL/Verilog13:49
lkclthere are already.... 15 compile-time options in issuer_verilog.py13:49
lkclincluding ones that cut back the L1 Cache sizes to fit into 45k LUT4 ECP5s13:50
lkclif there are decent boards out there in the future with Libre/Open tools we'll be able to increase the capabilities that will fit13:51
lkclfor example i have a Digilent Nexys Video, it has an A7 *200t* (not a 100t like in the Arty A7)13:51
lkclthe only reason i got it is because of nextpnr-xilinx13:51
lkcloctavius, did you email NLnet your name/address? i did bcc you on that one, didn't i?13:52
ManiliNo I didn't do that yet. What should I do?13:53
octaviusNo, lkcl, I'll do that now13:54
lkcloctavius, yes please13:54
ManiliOh sorry...13:54
lkclManili, the convention is to put a person's name to ping them.  irc clients pick up on that and generate (annoying) attention-grabbing alerts13:55
lkcli disabled *all* of them in hexchat because they piss me off :)13:55
ManiliWell, that's hard for me to keep up with you guys. I'm from Slack planet, after all. :)13:56
lkcljoooy :)13:57
octaviuslkcl: Actually I don't know which email to use? Is it the usual one we used for RFP submission?13:57
lkclwhat's that?  that's a Libre / FOSS system, right? :)13:57
lkcloctavius, no13:57
lkcl1 sec13:57
octaviusManili: I joined the proj in Sep, took me a few months to get the hang of it (I still don't know most of the IRC etiquette/commands ;) )13:58
lkcloctavius, fwded13:58
octaviusthnx lkcl13:58
lkclManili, if you prefer a web client then you can register with matrix13:58
lkcland they've established an automatic bridge to libera.chat13:58
lkclwhich is why you see a lot of people with "[m]" on the end of their irc handle13:59
Manilioctavius :D13:59
Manililkcl, I'll give it a try. thx13:59
octaviusI simply copied luke and use Hexchat, though matrix saves the message history when you're offline14:00
markoslkcl, speaking of the nexys, did you try it at all?14:00
lkclmarkos, haven't had time yet!14:01
markos+1 hexchat14:01
lkclit's not going to be hard: a single entry in nmigen-boards based on existing pinouts from other projects14:02
lkclwhich has been done repeatedly and frequently14:02
markosthese days I'm finishing a diy made-from-plywood 20U rack closet and when done with that, I plan to get the nexys up and running14:03
markoslots of cables everywhere atm14:03
lkclManili, nice board.  200k FPGA.14:04
ManiliThere is a company in my country which creates FPGA boards with multiple Virtex 7series on. Could be a good candidate for our goals.14:07
ManiliBTW, Nexy is really nice.14:07
lkclyou mean nexys-4?14:08
lkclit's only a 100t - nice as it is - and is superceded by the Arty A714:08
lkclwhich has 4 PMODs14:09
lkcli got *two* 1bitsquared HyperRAM PMODs which makes startup a hell of a lot easier14:09
ManiliIs it possible to use open-source tools to program it?14:10
lkclyes, i've been using nextpnr-xilinx.  symbiflow also worked but it is 6x slower to route14:11
ManiliHave you ever tested SymbiFlow on 7-series?14:11
lkclyes. it's... ok.14:13
lkclsome of the IO types are not supported (LVDS, DDR)14:13
lkclwhere they are by nextpnr-xilinx14:14
lkclboth are "broken" as far as adds/subs/cmps greater than 4*26-bits in length14:14
lkclyou have to "compensate" for that by adding "-nocarrylut" to yosys14:14
lkclwhich results in a "punishment" of a drop in speed of 30%14:15
lkcllong story, look it up online.14:15
Manililkcl, Great info. Thanks a lot. I'm ganna look deep into the links which you provided earlier about the multi-core ISA emulator and then I'll be right back to you.14:17
lkclManili, no problem. Peter Hsu is amazing.  he was the designer of the MIPS R8000.14:18
lkclghostmansd[m], how you getting on? i'm trying to think how to get you out of a binutils bottomless pit :)14:37
lkclyou saw it occurred to me (at 6am sigh) that sm=1<<r3 is, realistically, never going to be suitable for macros?14:38
lkcl(or, sm=u3, or, sm=the-unary-r3)14:39
ghostmansd[m]That's OK, I almost see the light in the end of the tunnel :-)14:39
ghostmansd[m]Do you mean that anyone who's going to use it will anyway use it w/o macros?14:44
ghostmansd[m]I started implementing all predicates, I'm only not quite sure how to organize it better.14:50
ghostmansd[m]As for 1<<r3...
lkclghostmansd[m], sm=^%r3 works for me. it's even shorter than sm=1<<r315:20
ghostmansd[m]Shorter for you doesn't imply shorter code in binutils :-)15:21
ghostmansd[m]Likely there's no such operator15:21
ghostmansd[m]But perhaps it's even more evident that this one is special, and at least it follows the same conventions as everything else15:24
octaviuslkcl, it compiles :D16:49
octaviusI had to edit the #include statements (tcl.h is now under tcl/tcl.h)16:49
lkcloctavius, hooraay.19:06
lkclok put that on the bugreport if you haven't already19:06
lkcli'll raise the issue with jean-paul19:07
tplatenI have read it is an interesting article19:09
lkclyes, some good tips on it19:10
tplatencurrently looking at Cesar's patch from ten days ago.19:14
tplatenFirst I modify src/ to pass a flag to enable the ECLKBRIDGECS. That will be false by default19:35
octaviusHi lkcl, I won't be available this evening for the meeting. My uncle has arrived (he's a sailor!) so I better use the opportunity to spend time together:D21:11
lkclprogrammerjake, meeting ^22:04

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