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| Ritish | rawr | 04:49 |
|---|---|---|
| Ritish | Happy Christmas eve | 04:50 |
| Ritish | Have fun peeps ^^ | 04:50 |
| lkcl | thx Ritish you too | 04:56 |
| Ritish | Thanks Luke :) | 05:02 |
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| Ritish | lkcl, I might need help in figuring out which instructions are scalar and which are vector, so that I can combine a code repository for libresoc lite. If you have time to explain, would be grateful :D | 08:46 |
| Ritish | aight, this is what I was looking for O.O | 09:13 |
| Ritish | https://libre-soc.org/openpower/sv/ | 09:13 |
| Ritish | probably | 09:14 |
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| openpowerbot | [mattermost] <lkcl> Ritish: the Vectorisation is a prefix system. disable the prefix system and Vectorisation is gone. dead simple. | 12:07 |
| openpowerbot | [mattermost] <lkcl> all you need to do is compile the libre-soc core with "--disable-svp64". | 12:07 |
| openpowerbot | [mattermost] <lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=Makefile;h=2a6409b663126891d5d8b3687aca4598551fbdd4;hb=a4bde05025e6583c49942c05c4caaee0e12c1768#l50 | 12:08 |
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| Ritish | Okay, that makes things simpler for me. I mean isn't that way too convenient haha. Alright I shall do the needy now hm hm | 13:18 |
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| openpowerbot | [mattermost] <lkcl> you can use the automated build scripts. https://libre-soc.org/HDL_workflow/devscripts/ | 13:37 |
| openpowerbot | [mattermost] <lkcl> bear in mind that there's a 100% track record of everyone who *doesn't* use the build scripts failing to complete installation, wasting at least 3 weeks of their time in the process | 13:38 |
| openpowerbot | [mattermost] <lkcl> and most people using the automated install scripts report completion successfully in 24-48 hours. | 13:39 |
| openpowerbot | [mattermost] <lkcl> also: the soclayout TSMC 180nm which was taped out has a tag already for the final version used. | 13:40 |
| openpowerbot | [mattermost] <lkcl> jean-paul wanted the auto-built verilog, it breaks all the rules about never under any circumstances committing auto-generated code to any repository | 13:41 |
| openpowerbot | [mattermost] <lkcl> but it cut such a vast amount of time for jean-paul that we decided to do it | 13:41 |
| openpowerbot | [mattermost] <lkcl> (and ended up being "punished" with a repo 100x larger than the source code that it was built from) | 13:41 |
| openpowerbot | [mattermost] <lkcl> sigh | 13:42 |
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| Ritish | lkcl, I actually just finished installing the build scripts today, haha :) | 16:06 |
| Ritish | one question, how do I test if my files have installed successfully, like, what is the command to run libresoc or smth like that :0 | 16:08 |
| lkcl | nice! | 16:09 |
| Ritish | So, if something gets easier on one end, it gets harder on the other, I see hm hm. Now the repo is harder to navigate I assume. Atleast it is for me haha | 16:10 |
| lkcl | you can usually run "make test" but be prepared for that to take a pretty long time in openpower-isa | 16:10 |
| lkcl | it's a 150,000 line software engineered project | 16:10 |
| lkcl | you should adapt your expectations accordingly. | 16:11 |
| Ritish | oops, gonna have to do that when I'm more free then haha | 16:11 |
| Ritish | Gotchu | 16:11 |
| lkcl | other FOSSHW projects, typically RISC-V, will be far smaller because there's 25% the number of instructions and they typically don't bother to do Virtual Memory and an MMU | 16:12 |
| Ritish | I see | 16:12 |
| lkcl | https://libre-soc.org/docs/ | 16:13 |
| lkcl | there's some "getting started" things there | 16:13 |
| lkcl | you also have to understand that this has been a bootstrapped project which used python unit tests at *every* level | 16:13 |
| Ritish | Gotchu | 16:14 |
| lkcl | unlike other FOSSHW projects which, if you look closely, you find literally no evidence of module-level unit tests of any kind | 16:14 |
| lkcl | it's as if they wrote the entire design first, then relied almost exclusively on systems-level tests to get the *entire* design working | 16:15 |
| Ritish | if I may ask what exactly are FOSSHW projects | 16:15 |
| Ritish | sounds like typical academic projects to me hmm | 16:15 |
| lkcl | Free and Open Source Hardware | 16:15 |
| Ritish | okii | 16:16 |
| lkcl | basically, the entire project has been so large and so complex that the only way to "manage" it - to gain understanding and confirm correct functionality - absolutely *had* to be by writing unit tests | 16:16 |
| lkcl | i ported the Microwatt L1 I-Cache and D-Cache and MMU to nmigen for example | 16:17 |
| lkcl | it took 3 people 18 months | 16:17 |
| Ritish | yesss, I did observe that | 16:17 |
| Ritish | omg | 16:17 |
| Ritish | haha | 16:17 |
| lkcl | and required approximately 25 separate unit tests | 16:17 |
| lkcl | finally | 16:17 |
| lkcl | after all that | 16:17 |
| lkcl | i was in a position to run the microwatt mmu.bin program | 16:18 |
| Ritish | oof | 16:18 |
| Ritish | worth it? | 16:18 |
| Ritish | 18 months is a lot | 16:18 |
| lkcl | which then led to 4 *more* weeks of debugging and writing more unit tests in order to track down very obscure bugs | 16:18 |
| Ritish | I seee | 16:18 |
| lkcl | if we had more people it would have been done far, far quicker | 16:19 |
| lkcl | i have a strange form of dyslexia involving logic | 16:19 |
| lkcl | if you put two similar-looking concepts / variables in front of me i have difficulty discerning them (BFP16, bfloat16, FP16) | 16:20 |
| lkcl | whereas someone else would know instantly which is which | 16:20 |
| Ritish | I see, I'm sorry to hear that. But we're here for you mate! | 16:20 |
| lkcl | unit tests were the *only* way to make sure that things could be confirmed working and stay working | 16:21 |
| Ritish | I understand | 16:21 |
| lkcl | hey it's fine - i'm used to it, used to compensating | 16:21 |
| lkcl | > "worth it"? | 16:21 |
| lkcl | the goal is the goal - to create a Hybrid 3D CPU / GPU / VPU | 16:22 |
| lkcl | anything that gets towards that goal is inherently "worth it" | 16:22 |
| Ritish | ahaha, you say that, but I couldn't imagine myself in your position :) | 16:22 |
| Ritish | gotchu | 16:22 |
| lkcl | :) | 16:22 |
| Ritish | cache for more processing speed? | 16:22 |
| lkcl | it will help explain why there is not "a one pipeline with everything in it" | 16:23 |
| lkcl | microwatt's pass-through L1 caches at the moment (ported to nmigen) | 16:23 |
| Ritish | do we have any other cache in libresoc other than microwatt's | 16:23 |
| lkcl | because the job of writing a L1 cache is hard enough as it is | 16:23 |
| Ritish | I bet it is | 16:23 |
| lkcl | we basically bootstrapped up off of the expertise behind the IBM Research Team | 16:24 |
| Ritish | Hmm! | 16:24 |
| lkcl | Power ISA is... a lot to take in at once | 16:24 |
| lkcl | i mean it's designed for supercomputing, for goodness sake | 16:24 |
| lkcl | like, in talking with paul mackerras a couple months back about atomic instructions | 16:25 |
| Ritish | I agree :/.. I was trying to see it's datasheet (or whatever it is called) to convert microwatt vhdl to ISA instructions. But I had to give up. | 16:25 |
| lkcl | we found out that there is *one* expert inside IBM who has literally spent years designing the atomic operations used in the Power ISA | 16:26 |
| lkcl | to make sure that they scale from 2 cores to 64 cores to half a MMMILLLION cores | 16:26 |
| Ritish | woah | 16:26 |
| Ritish | and is that sir Peter Hofstee | 16:27 |
| lkcl | because if you have a Supercomputing ISA, you absolutely have to have atomic memory operations that don't choke by the time you get to say 8 cores | 16:27 |
| lkcl | honestly i don't know. if it is, then that's really good news | 16:27 |
| Ritish | I seee. Alrighty | 16:27 |
| Ritish | (Also, Am I disturbing your sequence of your messages, because people reading it later will find it hard to understand, or so I feel) | 16:28 |
| lkcl | naah i'm just yakkin :) | 16:28 |
| lkcl | might have to get up and walk about in a bit | 16:28 |
| lkcl | btw you know you can use matrix, and also there's the OPF mattermost bridge, right? | 16:29 |
| Ritish | ahahaa, then me be chill ;) | 16:29 |
| lkcl | https://chat.openpower.foundation/opf/channels/libre-soc | 16:29 |
| Ritish | I didn't know, but thanks! | 16:29 |
| lkcl | if you encounter bayigal on here do ping him this | 16:30 |
| lkcl | https://libre-soc.org/irclog/%23libre-soc.2022-12-16.log.html#t2022-12-16T20:26:23 | 16:30 |
| Ritish | sure :) | 16:30 |
| Ritish | It's bagiyal I think btw haha | 16:31 |
| lkcl | he's obviously not able to maintain a permanent internet connection | 16:31 |
| Ritish | yupp | 16:31 |
| lkcl | btw if you get... ahh... what is it... python-sphinx installed | 16:31 |
| lkcl | you can rebuild the sphinx-doc stuff locally | 16:32 |
| Ritish | ohh, alright! | 16:32 |
| lkcl | which will give you the ability to navigate the source trees | 16:32 |
| lkcl | i ran this version... err... 18 months ago? https://docs.libre-soc.org/soc/ | 16:32 |
| Ritish | that makes stuff easier, noice | 16:32 |
| lkcl | which is still relevant, as there's not been much development since the 180nm ASIC | 16:33 |
| lkcl | that's linked off of here https://libre-soc.org/docs/ | 16:33 |
| lkcl | it's all there | 16:33 |
| lkcl | you just have to get used to the fact that "it's not github github github github github" | 16:33 |
| lkcl | you know what i mean :) | 16:34 |
| Ritish | sure do :) | 16:34 |
| Ritish | I have bagiyal's discord, so I shall explain him there | 16:34 |
| lkcl | ok awesome | 16:34 |
| Ritish | aye! | 16:35 |
| Ritish | back to the "make test" command | 16:35 |
| Ritish | should I do it inside the "sudo bash" thingy | 16:36 |
| Ritish | or would normal terminal do | 16:36 |
| Ritish | inside the directory "dev-env-setup" I assume | 16:36 |
| lkcl | well ymmv | 16:38 |
| Ritish | Hmm | 16:38 |
| lkcl | i navigate to the "openpower-isa/src/openpower/decoder/isa" directory | 16:39 |
| lkcl | then run "nohup nice -20 pytest-3 -v -n 8" | 16:39 |
| lkcl | (8 threads, there) | 16:39 |
| Ritish | I seee | 16:39 |
| lkcl | because that's where my current focus is | 16:39 |
| Ritish | alrighty | 16:39 |
| Ritish | "me imagining a command has "nice" in it" xD | 16:40 |
| lkcl | in the soc repo you could do this | 16:40 |
| lkcl | python3 simple/test/test_issuer.py nosvp64 shiftrot shiftrot2 >& /tmp/f1 | 16:40 |
| lkcl | or | 16:41 |
| lkcl | python3 simple/test/test_issuer.py nosvp64 mul >& /tmp/f1 | 16:41 |
| lkcl | and examine the unit test itself to see what's going on | 16:41 |
| lkcl | btw, now would be a good time to consider adapting your working practices to get the absolute maximum number of terminals on-screen as you can possibly fit | 16:42 |
| Ritish | o..okayy haha | 16:42 |
| lkcl | https://libre-soc.org/HDL_workflow/2020-01-24_11-56.png | 16:42 |
| Ritish | me gon have to experiment | 16:42 |
| Ritish | I did see this, but can't imagine that was all at once | 16:43 |
| Ritish | btwww | 16:43 |
| Ritish | I HAVE A DOUBT | 16:43 |
| Ritish | sorry on the caps | 16:43 |
| Ritish | but | 16:43 |
| lkcl | if you are expecting to do the usual "i'll just open this one file full-screen on my 1920x1080 or 3840x2140 monitor" | 16:43 |
| lkcl | and expect from that to have a hope in hell of navigating anything at all | 16:43 |
| lkcl | then you are sorely mistaken | 16:43 |
| Ritish | Do you visualize the code or architecture whenever you are explaining stuff to someone. Like is everything actually recorded in your mind | 16:44 |
| lkcl | the maximum number of vim sessions i've ever had open at once is one thousand SIX HUNDRED. | 16:44 |
| lkcl | it's... basically subconscious, due to the dyslexia | 16:44 |
| lkcl | and some very strange memory issues | 16:44 |
| Ritish | 600, you're lying xD (no, I believe you, kiddin!) | 16:45 |
| Ritish | I see :) | 16:45 |
| lkcl | no, one *thousand* six hundred | 16:45 |
| Ritish | ehmm | 16:45 |
| lkcl | if i try to memorise something i can't remember something from six seconds ago | 16:45 |
| Ritish | gotchu | 16:45 |
| lkcl | unless i have looked at it ten, fifteen, thirty times | 16:45 |
| Ritish | aww :/ | 16:46 |
| lkcl | therefore putting things side-by-side on the same screen is absolutely essential for me. | 16:46 |
| lkcl | then there's a class hierarchy, so i have to open another terminal | 16:46 |
| lkcl | then that uses something so i have to open another one | 16:46 |
| lkcl | ... | 16:46 |
| lkcl | ... | 16:46 |
| Ritish | then how do you manage to learn. maybe a tip or two for me? | 16:47 |
| lkcl | but what's really weird is that after a few days/weeks it all goes into *long-term* memory | 16:47 |
| Ritish | nice! | 16:47 |
| lkcl | persistence. | 16:47 |
| lkcl | sheer bloody-minded persistence | 16:47 |
| Ritish | okay | 16:47 |
| Ritish | something I need to develop, I would say | 16:47 |
| Ritish | I am easily distracted | 16:48 |
| lkcl | the goal is the goal: absolute patience stems from the decision of the goal | 16:48 |
| lkcl | me too | 16:48 |
| lkcl | it's an engineering mindset | 16:48 |
| Ritish | Hmmm | 16:48 |
| lkcl | "i don't know how to do this therefore i'm going to find out" | 16:48 |
| lkcl | rather than | 16:49 |
| lkcl | "i don't know how to do this therefore i'm going to fail and/or just not bother" | 16:49 |
| Ritish | right | 16:49 |
| Ritish | I have to take the right choice | 16:49 |
| Ritish | I often run away from complex stuff | 16:49 |
| lkcl | it doesn't matter if you didn't make _much_ progress, as long as you made some. | 16:49 |
| Ritish | or try to | 16:49 |
| lkcl | that's perfectly understandable | 16:49 |
| lkcl | but if you chip at it a piece at a time, break it into smaller parts, it becomes manageable | 16:50 |
| Ritish | That line says a lot | 16:50 |
| lkcl | and look for what other people have done, and bootstrap up. | 16:50 |
| lkcl | Power ISA is *horribly* complex, to me | 16:50 |
| lkcl | therefore i tracked down the world's leading experts in it, and made sure to use their HDL literally line-for-line | 16:51 |
| Ritish | what in your word would "bootstrap up" mean | 16:51 |
| Ritish | gotchu | 16:51 |
| lkcl | translated from VHDL into nmigen *literally* line-for-line | 16:51 |
| Ritish | damn | 16:51 |
| lkcl | mmu.vhdl is identical to mmu.py | 16:51 |
| Ritish | words* | 16:51 |
| Ritish | I see | 16:51 |
| lkcl | dcache.py is identical to dcache.vhdl from about 2 years ago | 16:51 |
| lkcl | i still don't *actually* fully understand it | 16:52 |
| lkcl | all i know is: the 25+ unit tests "work" | 16:52 |
| Ritish | interesting | 16:52 |
| Ritish | do you still spend time understanding it | 16:53 |
| lkcl | there's no point getting "judgemental" or "scared" or "i can't do it" about that | 16:53 |
| lkcl | hell no | 16:53 |
| lkcl | it does the job, i moved on *very* quickly :) | 16:53 |
| lkcl | if we *need* a more complex cache, that's the point at which we "need to get back into it" | 16:53 |
| lkcl | yeh? | 16:53 |
| lkcl | it's about being practical and pragmatic, doing the things you _can_ do and being very pathological about the things you can't | 16:54 |
| lkcl | don't understand the cache? don't care. does it pass the tests, yes/no. yes: great. move on. | 16:54 |
| lkcl | next task please | 16:55 |
| lkcl | yeh? :) | 16:55 |
| lkcl | i'm overstating things: i do actually understand how it works, at a high-level | 16:55 |
| lkcl | you can't "not" gain a basic grasp of it after working with it for 18 months, if you know what i mean | 16:56 |
| Ritish | yeh! | 16:56 |
| lkcl | anyway. have to get up and walk about. | 16:56 |
| Ritish | Thanks for all that Luke ^^ | 16:56 |
| Ritish | Imma have this page bookmarked :) | 16:57 |
| Ritish | Have a good time! Merry quismas xD | 16:57 |
| lkcl | no problem. you too | 16:58 |
| Ritish | Thank you <3 | 16:59 |
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