Saturday, 2022-12-24

*** Ritish <Ritish!~Ritish@> has joined #libre-soc04:47
RitishHappy Christmas eve04:50
RitishHave fun peeps ^^04:50
lkclthx Ritish you too04:56
RitishThanks Luke :)05:02
*** sai_ <sai_!~Ritish@> has joined #libre-soc07:01
*** Ritish <Ritish!~Ritish@> has quit IRC07:04
*** sai_ is now known as Ritish07:51
Ritishlkcl, I might need help in figuring out which instructions are scalar and which are vector, so that I can combine a code repository for libresoc lite. If you have time to explain, would be grateful :D08:46
Ritishaight, this is what I was looking for O.O09:13
*** Ritish <Ritish!~Ritish@> has quit IRC09:58
*** Ritish <Ritish!~Ritish@> has joined #libre-soc09:58
*** Ritish <Ritish!~Ritish@> has quit IRC10:00
*** Ritish <Ritish!~Ritish@> has joined #libre-soc10:51
*** Ritish <Ritish!~Ritish@> has quit IRC11:01
*** ghostmansd[m] <ghostmansd[m]!> has quit IRC11:01
*** ghostmansd[m] <ghostmansd[m]!~ghostmans@> has joined #libre-soc11:02
*** markos <markos!> has quit IRC11:06
openpowerbot[mattermost] <lkcl> Ritish: the Vectorisation is a prefix system.  disable the prefix system and Vectorisation is gone.  dead simple.12:07
openpowerbot[mattermost] <lkcl> all you need to do is compile the libre-soc core with "--disable-svp64".12:07
openpowerbot[mattermost] <lkcl>;a=blob;f=Makefile;h=2a6409b663126891d5d8b3687aca4598551fbdd4;hb=a4bde05025e6583c49942c05c4caaee0e12c1768#l5012:08
*** Ritish <Ritish!~Ritish@2401:4900:6273:9913:dec9:ba60:4b75:d89d> has joined #libre-soc13:17
RitishOkay, that makes things simpler for me. I mean isn't that way too convenient haha. Alright I shall do the needy now hm hm13:18
*** ghostmansd[m] <ghostmansd[m]!~ghostmans@> has quit IRC13:21
*** ghostmansd[m] <ghostmansd[m]!~ghostmans@> has joined #libre-soc13:22
*** Ritish <Ritish!~Ritish@2401:4900:6273:9913:dec9:ba60:4b75:d89d> has quit IRC13:25
openpowerbot[mattermost] <lkcl> you can use the automated build scripts.
openpowerbot[mattermost] <lkcl> bear in mind that there's a 100% track record of everyone who *doesn't* use the build scripts failing to complete installation, wasting at least 3 weeks of their time in the process13:38
openpowerbot[mattermost] <lkcl> and most people using the automated install scripts report completion successfully in 24-48 hours.13:39
openpowerbot[mattermost] <lkcl> also: the soclayout TSMC 180nm which was taped out has a tag already for the final version used.13:40
openpowerbot[mattermost] <lkcl> jean-paul wanted the auto-built verilog, it breaks all the rules about never under any circumstances committing auto-generated code to any repository13:41
openpowerbot[mattermost] <lkcl> but it cut such a vast amount of time for jean-paul that we decided to do it13:41
openpowerbot[mattermost] <lkcl> (and ended up being "punished" with a repo 100x larger than the source code that it was built from)13:41
openpowerbot[mattermost] <lkcl> sigh13:42
*** Ritish <Ritish!~Ritish@2402:e280:2156:31:95e0:8357:a8ea:1f23> has joined #libre-soc16:04
Ritishlkcl, I actually just finished installing the build scripts today, haha :)16:06
Ritishone question, how do I test if my files have installed successfully, like, what is the command to run libresoc or smth like that :016:08
RitishSo, if something gets easier on one end, it gets harder on the other, I see hm hm. Now the repo is harder to navigate I assume. Atleast it is for me haha16:10
lkclyou can usually run "make test" but be prepared for that to take a pretty long time in openpower-isa16:10
lkclit's a 150,000 line software engineered project16:10
lkclyou should adapt your expectations accordingly.16:11
Ritishoops, gonna have to do that when I'm more free then haha16:11
lkclother FOSSHW projects, typically RISC-V, will be far smaller because there's 25% the number of instructions and they typically don't bother to do Virtual Memory and an MMU16:12
RitishI see16:12
lkclthere's some "getting started" things there16:13
lkclyou also have to understand that this has been a bootstrapped project which used python unit tests at *every* level16:13
lkclunlike other FOSSHW projects which, if you look closely, you find literally no evidence of module-level unit tests of any kind16:14
lkclit's as if they wrote the entire design first, then relied almost exclusively on systems-level tests to get the *entire* design working16:15
Ritishif I may ask what exactly are FOSSHW projects16:15
Ritishsounds like typical academic projects to me hmm16:15
lkclFree and Open Source Hardware16:15
lkclbasically, the entire project has been so large and so complex that the only way to "manage" it - to gain understanding and confirm correct functionality - absolutely *had* to be by writing unit tests16:16
lkcli ported the Microwatt L1 I-Cache and D-Cache and MMU to nmigen for example16:17
lkclit took 3 people 18 months16:17
Ritishyesss, I did observe that16:17
lkcland required approximately 25 separate unit tests16:17
lkclafter all that16:17
lkcli was in a position to run the microwatt mmu.bin program16:18
Ritishworth it?16:18
Ritish18 months is a lot16:18
lkclwhich then led to 4 *more* weeks of debugging and writing more unit tests in order to track down very obscure bugs16:18
RitishI seee16:18
lkclif we had more people it would have been done far, far quicker16:19
lkcli have a strange form of dyslexia involving logic16:19
lkclif you put two similar-looking concepts / variables in front of me i have difficulty discerning them (BFP16, bfloat16, FP16)16:20
lkclwhereas someone else would know instantly which is which16:20
RitishI see, I'm sorry to hear that. But we're here for you mate!16:20
lkclunit tests were the *only* way to make sure that things could be confirmed working and stay working16:21
RitishI understand16:21
lkclhey it's fine - i'm used to it, used to compensating16:21
lkcl> "worth it"?16:21
lkclthe goal is the goal - to create a Hybrid 3D CPU / GPU / VPU16:22
lkclanything that gets towards that goal is inherently "worth it"16:22
Ritishahaha, you say that, but I couldn't imagine myself in your position :)16:22
Ritishcache for more processing speed?16:22
lkclit will help explain why there is not "a one pipeline with everything in it"16:23
lkclmicrowatt's pass-through L1 caches at the moment (ported to nmigen)16:23
Ritishdo we have any other cache in libresoc other than microwatt's16:23
lkclbecause the job of writing a L1 cache is hard enough as it is16:23
RitishI bet it is16:23
lkclwe basically bootstrapped up off of the expertise behind the IBM Research Team16:24
lkclPower ISA is... a lot to take in at once16:24
lkcli mean it's designed for supercomputing, for goodness sake16:24
lkcllike, in talking with paul mackerras a couple months back about atomic instructions16:25
RitishI agree :/.. I was trying to see it's datasheet (or whatever it is called) to convert microwatt vhdl to ISA instructions. But I had to give up.16:25
lkclwe found out that there is *one* expert inside IBM who has literally spent years designing the atomic operations used in the Power ISA16:26
lkclto make sure that they scale from 2 cores to 64 cores to half a MMMILLLION cores16:26
Ritishand is that sir Peter Hofstee16:27
lkclbecause if you have a Supercomputing ISA, you absolutely have to have atomic memory operations that don't choke by the time you get to say 8 cores16:27
lkclhonestly i don't know.  if it is, then that's really good news16:27
RitishI seee. Alrighty16:27
Ritish(Also, Am I disturbing your sequence of your messages, because people reading it later will find it hard to understand, or so I feel)16:28
lkclnaah i'm just yakkin :)16:28
lkclmight have to get up and walk about in a bit16:28
lkclbtw you know you can use matrix, and also there's the OPF mattermost bridge, right?16:29
Ritishahahaa, then me be chill ;)16:29
RitishI didn't know, but thanks!16:29
lkclif you encounter bayigal on here do ping him this16:30
Ritishsure :)16:30
RitishIt's bagiyal I think btw haha16:31
lkclhe's obviously not able to maintain a permanent internet connection16:31
lkclbtw if you get... ahh... what is it... python-sphinx installed16:31
lkclyou can rebuild the sphinx-doc stuff locally16:32
Ritishohh, alright!16:32
lkclwhich will give you the ability to navigate the source trees16:32
lkcli ran this version... err... 18 months ago?
Ritishthat makes stuff easier, noice16:32
lkclwhich is still relevant, as there's not been much development since the 180nm ASIC16:33
lkclthat's linked off of here
lkclit's all there16:33
lkclyou just have to get used to the fact that "it's not github github github github github"16:33
lkclyou know what i mean :)16:34
Ritishsure do :)16:34
RitishI have bagiyal's discord, so I shall explain him there16:34
lkclok awesome16:34
Ritishback to the "make test" command16:35
Ritishshould I do it inside the "sudo bash" thingy16:36
Ritishor would normal terminal do16:36
Ritishinside the directory "dev-env-setup" I assume16:36
lkclwell ymmv16:38
lkcli navigate to the "openpower-isa/src/openpower/decoder/isa" directory16:39
lkclthen run "nohup nice -20 pytest-3 -v -n 8"16:39
lkcl(8 threads, there)16:39
RitishI seee16:39
lkclbecause that's where my current focus is16:39
Ritish"me imagining a command has "nice" in it" xD16:40
lkclin the soc repo you could do this16:40
lkclpython3 simple/test/ nosvp64 shiftrot shiftrot2 >& /tmp/f116:40
lkclpython3 simple/test/ nosvp64 mul >& /tmp/f116:41
lkcland examine the unit test itself to see what's going on16:41
lkclbtw, now would be a good time to consider adapting your working practices to get the absolute maximum number of terminals on-screen as you can possibly fit16:42
Ritisho..okayy haha16:42
Ritishme gon have to experiment16:42
RitishI did see this, but can't imagine that was all at once16:43
RitishI HAVE A DOUBT16:43
Ritishsorry on the caps16:43
lkclif you are expecting to do the usual "i'll just open this one file full-screen on my 1920x1080 or 3840x2140 monitor"16:43
lkcland expect from that to have a hope in hell of navigating anything at all16:43
lkclthen you are sorely mistaken16:43
RitishDo you visualize the code or architecture whenever you are explaining stuff to someone. Like is everything actually recorded in your mind16:44
lkclthe maximum number of vim sessions i've ever had open at once is one thousand SIX HUNDRED.16:44
lkclit's... basically subconscious, due to the dyslexia16:44
lkcland some very strange memory issues16:44
Ritish600, you're lying xD (no, I believe you, kiddin!)16:45
RitishI see :)16:45
lkclno, one *thousand* six hundred16:45
lkclif i try to memorise something i can't remember something from six seconds ago16:45
lkclunless i have looked at it ten, fifteen, thirty times16:45
Ritishaww :/16:46
lkcltherefore putting things side-by-side on the same screen is absolutely essential for me.16:46
lkclthen there's a class hierarchy, so i have to open another terminal16:46
lkclthen that uses something so i have to open another one16:46
Ritishthen how do you manage to learn. maybe a tip or two for me?16:47
lkclbut what's really weird is that after a few days/weeks it all goes into *long-term* memory16:47
lkclsheer bloody-minded persistence16:47
Ritishsomething I need to develop, I would say16:47
RitishI am easily distracted16:48
lkclthe goal is the goal: absolute patience stems from the decision of the goal16:48
lkclme too16:48
lkclit's an engineering mindset16:48
lkcl"i don't know how to do this therefore i'm going to find out"16:48
lkclrather than16:49
lkcl"i don't know how to do this therefore i'm going to fail and/or just not bother"16:49
RitishI have to take the right choice16:49
RitishI often run away from complex stuff16:49
lkclit doesn't matter if you didn't make _much_ progress, as long as you made some.16:49
Ritishor try to16:49
lkclthat's perfectly understandable16:49
lkclbut if you chip at it a piece at a time, break it into smaller parts, it becomes manageable16:50
RitishThat line says a lot16:50
lkcland look for what other people have done, and bootstrap up.16:50
lkclPower ISA is *horribly* complex, to me16:50
lkcltherefore i tracked down the world's leading experts in it, and made sure to use their HDL literally line-for-line16:51
Ritishwhat in your word would "bootstrap up" mean16:51
lkcltranslated from VHDL into nmigen *literally* line-for-line16:51
lkclmmu.vhdl is identical to mmu.py16:51
RitishI see16:51 is identical to dcache.vhdl from about 2 years ago16:51
lkcli still don't *actually* fully understand it16:52
lkclall i know is: the 25+ unit tests "work"16:52
Ritishdo you still spend time understanding it16:53
lkclthere's no point getting "judgemental" or "scared" or "i can't do it" about that16:53
lkclhell no16:53
lkclit does the job, i moved on *very* quickly :)16:53
lkclif we *need* a more complex cache, that's the point at which we "need to get back into it"16:53
lkclit's about being practical and pragmatic, doing the things you _can_ do and being very pathological about the things you can't16:54
lkcldon't understand the cache? don't care. does it pass the tests, yes/no.  yes: great. move on.16:54
lkclnext task please16:55
lkclyeh? :)16:55
lkcli'm overstating things: i do actually understand how it works, at a high-level16:55
lkclyou can't "not" gain a basic grasp of it after working with it for 18 months, if you know what i mean16:56
lkclanyway. have to get up and walk about.16:56
RitishThanks for all that Luke ^^16:56
RitishImma have this page bookmarked :)16:57
RitishHave a good time! Merry quismas xD16:57
lkclno problem. you too16:58
RitishThank you <316:59
*** Ritish <Ritish!~Ritish@2402:e280:2156:31:95e0:8357:a8ea:1f23> has quit IRC17:03
*** ghostmansd[m] <ghostmansd[m]!~ghostmans@> has quit IRC17:20
*** ghostmansd[m] <ghostmansd[m]!> has joined #libre-soc17:21
*** lxo <lxo!~lxo@gateway/tor-sasl/lxo> has quit IRC22:03
*** lxo <lxo!~lxo@gateway/tor-sasl/lxo> has joined #libre-soc22:15

Generated by 2.17.1 by Marius Gedminas - find it at!