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| lkcl | programmerjake, the file-thing works great. still at 12 gb on 3.2.5 but that's perfectly fine | 12:40 |
|---|---|---|
| lkcl | nicely done | 12:40 |
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| octavius | lkcl, I've looked at the ls2 verilator sim today. Although I got the gtkwave traces printing and I can see the processor executing, I don't see the UART tx coming out to stdout. I expected this because the microwatt repo verilator sim does this. Has something changed between the microwatt and ls2 uart functions that redirects the uart tx somewhere else? | 13:38 |
| octavius | I compared the 'uart-verilator.cpp' drivers and 'microwatt-verilator.cpp' between microwatt and ls2 repos and found no significant difference | 13:39 |
| lkcl | i really don't know, it's been too long | 14:09 |
| lkcl | you'll need to trace the instructions one at a time | 14:10 |
| lkcl | you know the order of instructions from verilator | 14:10 |
| lkcl | ah uart-verilator.cpp is not a "driver" | 14:12 |
| lkcl | it is a c++ verilator... there's a special term for it | 14:12 |
| lkcl | model? | 14:12 |
| lkcl | no wait | 14:13 |
| lkcl | uart_tx and uart_rx are just "functions that do stuff which happens to emulate a 16550 UART" | 14:13 |
| lkcl | what you *actually* meant was, | 14:14 |
| lkcl | "at line 308 which is where uart_tx() is called, there *is* no data received that that function recognises" | 14:15 |
| lkcl | therefore, the most logical and obvious thing to do is: | 14:15 |
| lkcl | look at the input to uart_tx | 14:15 |
| lkcl | yes? | 14:15 |
| lkcl | that's the "information-discernment-point" | 14:16 |
| lkcl | you should have a model in your head "how this works" | 14:16 |
| lkcl | "what do i expect this to do, why is it not doing it, what is *producing* it so i can take a look at it" | 14:16 |
| lkcl | drill-down, drill-down, drill-down, drill-down... | 14:17 |
| lkcl | so | 14:17 |
| lkcl | uart_tx(top->uart0_txd); | 14:17 |
| lkcl | top->uart0_rxd = uart_rx(); | 14:17 |
| lkcl | what do you think goes in and out of those functions, yes? | 14:18 |
| lkcl | the data doesn't come from nowhere | 14:18 |
| lkcl | top-> .... oh! that's the verilator model! | 14:18 |
| lkcl | ah, i can look at the verilator gtkwave trace, i guess it's called "uart0_txd" and "uart0_rxd"? | 14:19 |
| lkcl | ah, yes! okay! what are those signals doing? | 14:19 |
| lkcl | well, they're are moving / are not moving | 14:19 |
| lkcl | hmm, i wonder why *that* is? | 14:19 |
| lkcl | and you have moved on to the next drill-down in the debugging chain | 14:20 |
| lkcl | next, next, next, next | 14:20 |
| lkcl | yes? | 14:20 |
| lkcl | basically you can't treat everything as "a black box expected to work 1st time" | 14:21 |
| lkcl | remember i taught you, you need to make comparisons (diffs) | 14:21 |
| lkcl | from known-good to known-bad | 14:22 |
| lkcl | but if the diff is too big | 14:22 |
| lkcl | you have to decrease the diff | 14:22 |
| lkcl | yes? | 14:22 |
| octavius | Ok, thanks.Looks like uart_0__tx remains at 1 (idle), while uart_0__rx remains at 0. | 15:09 |
| octavius | That's the signals inside the 'uart' module. | 15:10 |
| octavius | At the top level, tx_o and rx_i are both stuck at 1. | 15:10 |
| octavius | Will have a look at why | 15:10 |
| lkcl | so that's eliminated the line of enquiry "uart-verilator.cpp and/or microwatt-verilator.cpp must be faulty" | 15:20 |
| lkcl | which was an assumption that you made rather than a "hypothesis to be tested" | 15:20 |
| lkcl | testing _that_ hypothesis however would involve wiggling top->uart_tx manually | 15:21 |
| lkcl | and/or calling uart_tx(somethingsomething) | 15:21 |
| lkcl | i.e. you *can* insert deliberately-intrusive code that *actually* modifies the output | 16:00 |
| lkcl | cutting off "the other stuff even though it's running" | 16:00 |
| lkcl | and just use the verilator binary as "an easy in-situ way to test a hypothesis" | 16:01 |
| lkcl | aka "hack it" :) | 16:01 |
| lkcl | ghostmansd[m], i leave it with you to fix the renames (to remove the use of common python modules). | 16:26 |
| lkcl | i have no problem with what they are, as long as they are not common standard python module names | 16:26 |
| lkcl | i have to terminate working on investigating the Idx0/1/2/3 ValueError | 16:28 |
| ghostmansd[m] | Please check the comments, it's not something to be fixed. | 16:29 |
| lkcl | ghostmansd[m], i can't do any work | 16:30 |
| ghostmansd[m] | It's perfectly normal to have modules named as python modules, because, in general, we don't control what modules are there with each new version. | 16:30 |
| ghostmansd[m] | lkcl, just call the script via pysvp64db | 16:30 |
| ghostmansd[m] | Not python3 src/openpower/insndb/db.py | 16:31 |
| ghostmansd[m] | And that's it, the "issue" is fixed. | 16:31 |
| ghostmansd[m] | Yes it's a bogus behavior, described in PEP and acknowledged. Yes they demonstrate how to fix it. | 16:31 |
| lkcl | ghostmansd[m], i am in distress because i feel have not been heard | 16:32 |
| ghostmansd[m] | Our imports are correct, don't override the builtins and work with setup.py like charm. | 16:32 |
| lkcl | please can you make the requested renames to something that you are happy with | 16:32 |
| ghostmansd[m] | It's rather me than you | 16:32 |
| ghostmansd[m] | Or, well, haven't been "read" | 16:33 |
| ghostmansd[m] | I explained the rationale | 16:33 |
| lkcl | ghostmansd[m], i am not able to use the correct english words to explain | 16:33 |
| ghostmansd[m] | And, by the way, the way you do imports has much bigger chances for collisions | 16:33 |
| lkcl | i am in distress because i cannot... | 16:33 |
| lkcl | i cannot explain properly | 16:34 |
| lkcl | and i cannot do any work | 16:34 |
| lkcl | that means that as the project leader if you have stopped me from being able to work it is extremely serious | 16:34 |
| ghostmansd[m] | No I don't stop | 16:34 |
| lkcl | far more serious than any "policy" or "process" | 16:34 |
| ghostmansd[m] | Again, you did setup.py? | 16:34 |
| lkcl | please | 16:35 |
| ghostmansd[m] | Then everything works | 16:35 |
| lkcl | please | 16:35 |
| lkcl | i am in distress | 16:35 |
| lkcl | i cannot work | 16:35 |
| lkcl | i have complex work to do | 16:35 |
| lkcl | i cannot do it | 16:35 |
| ghostmansd[m] | The thing is, you asking to fix something which never been broken and _wroks_ | 16:35 |
| ghostmansd[m] | Ok | 16:35 |
| ghostmansd[m] | I'll rename these | 16:35 |
| lkcl | this is more important than policies | 16:35 |
| ghostmansd[m] | But you know what? Fuck it. I'm in distress too. | 16:35 |
| lkcl | i know | 16:36 |
| ghostmansd[m] | So to keep your work I'm renaming this and leaving this to you. I'm pretty much fed up with this. | 16:36 |
| ghostmansd[m] | You don't even listen or read anything I write. Took about an hour to provide rationale to be never read. | 16:37 |
| ghostmansd[m] | Fine, just fine. | 16:37 |
| lkcl | i'm so sorry - i am currently trying to stabilise the spec | 16:38 |
| lkcl | and am under time-pressure because the ISA WG Chair is retiring | 16:38 |
| ghostmansd[m] | You don't listen. I explained several times why it's not an issue. But you just don't listen. | 16:38 |
| lkcl | so it's not "deliberately not listening" | 16:39 |
| lkcl | it's not like last year when there was no time-pressure, and i could focus on working with you | 16:39 |
| lkcl | okok | 16:40 |
| lkcl | don't make any changes | 16:40 |
| lkcl | let's do one thing at a time. | 16:42 |
| ghostmansd[m] | too late, it's disasm now | 16:44 |
| ghostmansd[m] | Run $(python3 src/openpower/insndb/db.py), it works | 16:45 |
| ghostmansd[m] | I'm shutting for a while, otherwise I'll say something rude and bad | 16:46 |
| ghostmansd[m] | I need to think about something else and be distracted by something less moving | 16:48 |
| ghostmansd[m] | ttyl | 16:48 |
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