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| programmerjake | I moved all the generated files (except all.py) in openpower.decoder.isa to their own directory so we don't have to worry about all the .mdwn file names conflicting with a non-generated file | 02:35 |
|---|---|---|
| programmerjake | this way we can change to a file-per-instruction so we can include them in the wiki to have one source for the pseudocode instead of copying it everywhere | 02:36 |
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| lkcl | programmerjake, thx for reviewing. everyone we need to move expediently on this but i cannot be the one to do it, i will explain on tuesday (tomorrow) | 09:57 |
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| octavius | Been busy for a few days, coming back to the problem I mentioned on Thursday with generating external core with SVP64 (see irc log: https://libre-soc.org/irclog/%23libre-soc.2023-07-27.log.html#t2023-07-27T18:03:34) | 13:44 |
| octavius | This commit on 24th June 2021 shows the 'use_svp64_ldst_dec' signal being added): https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=847075a69e38b96376b7db0d5df0cc125da0be7a | 13:44 |
| octavius | A commit on the 12th August 2022 then removes this signal: https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=fdba782098076205d7740fc091d925d63b29a194 | 13:44 |
| octavius | Using openpower-isa commit #1bbfcce929c9a1d6b1dc0fc68c84296bcc58eea1, I was able to generate an external core with the SVP64 enabled. | 13:44 |
| octavius | To compare the modules included in the verilog files, I used yosys' 'ls' utility and then ran a diff (external microwatt compatible on the left, external MW + SVP64 on the right): https://pastebin.com/Fw3QNPux | 13:44 |
| octavius | Will try this core in ls2 peripheral interconnect. | 13:44 |
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| octavius | During the synthesis of the core, errors regarding combinatorial loops occurred: | 14:47 |
| octavius | ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc. | 14:48 |
| octavius | 0 warnings, 1 error | 14:48 |
| octavius | The errors occur in dec2, and mostly due to the sv modules. | 14:48 |
| octavius | Full log running 'python3 src/ls2.py arty_a7 hello_world.bin' is here: https://pastebin.com/xc2hWTwG | 14:48 |
| octavius | lkcl, programmerjake, any ideas how to get this working? | 14:48 |
| octavius | Perhaps I'm generating the external core incorrectly. I wanted to maintain compatibility with Microwatt while also including the SVP64 hardware. | 14:48 |
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