Tuesday, 2022-03-29

programmerjakei published v0.3.0 of algebraics, thanks to some generous contributors who ported it to newer dependency versions so it works on stable rust02:29
programmerjake(used by simple-soft-float, the library i wrote as a reference for testing our fpu)02:29
markoshello, I could not fix the sv.ld error yesterday, thought I had an old tree so did a git pull everywhere, and now getting a sphinx missing module error:08:04
markosCould not import extension sphinxcontrib_verilog_diagrams (exception: No module named 'sphinxcontrib_verilog_diagrams')08:04
markosI could not find such a package08:05
programmerjakeapparently it was renamed:08:09
programmerjake> Renamed to https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams08:09
markosthe build environment seems too fragile imho, too many things can break08:43
programmerjakeyeah, i agree, but we don't really have time right now to redo everything to make it better08:44
markosand I'm not entirely sure in what order I  am supposed to fix those08:44
markosI would suggest a small debian repo with CI built packages08:44
programmerjakeI'm working on setting up CI right now...08:44
markoshaving a CI that builds newer versions of the packages would be a great boost -they don't have to follow all strict Debian guidelines, but they would certainly help in development08:46
markoswe had a similar system at my previous company08:46
markosif a PR would pass all CI tests, the CI itself would build and upload a new version of the package08:46
programmerjakecan you submit a bug so we don't forget to set up something like that?08:46
markosie, no need for manual uploads08:46
markoshttps://bugs.libre-soc.org/ ?08:47
markosok, I can see the login page, but where is the register page? :)08:48
programmerjakeicr if just anyone can make an account, or if an admin has to make you an account...let me know...08:48
markosI've used bugzilla in other projects, I could definitely register, there is/was a "New Account" link right next to Log In08:50
markosso I guess it's disabled08:50
markoslkcl, ^08:50
programmerjakeah, i'll make you a user account...08:51
programmerjakeicr what your email is...08:52
programmerjakemarkos: ^08:53
programmerjake@markos you should be able to reset your password now...let me know if it works08:58
markosprogrammerjake, done, which component would you like this bug reported to?09:09
programmerjakelibre-soc website should be good enough, we can move it to a better one if there is one09:11
markosnow to fix my own problem, after doing a git pull on all projects, how do I update the build system? I still get the sphinxcontrib_verilog_diagrams error and I still get the unrecognized opcode 'sv.ld' even though I'm 100% certain that the instruction is correct09:15
programmerjakei'd suspect you just have to change sphinxcontrib_verilog_diagrams to sphinxcontrib_hdl_diagrams...09:16
programmerjakefor the 'sv.ld' problem...that needs to be passed through SVP64Asm which converts it into instructions debian's version of gas understands:09:20
markosyes, I know, some instructions do get translated fine09:20
markosit's just this particular one that fails09:20
programmerjakeit's possible sv.ld wasn't yet added to SVP64Asm09:20
programmerjakei didn't see it, though I didn't go through SVP64Asm in detail rn09:21
programmerjakeall the load/store instructions need to be translated differently than the alu instructions, so that's probably why it doesn't work09:21
markosI see that "sv.ld 5.v, 4(1.v)" already in src/openpower/sv/trans/svp64.py09:22
markosand I'm trying 'sv.ld 10.v, 0(5.v)'09:23
programmerjakeit appears to work for me when i edit it into the main stuff at the bottom of svp64.py09:29
programmerjakeit gives `['.long 0x5403500', 'ld 2, 0(1)']`09:29
markosthis is the snippet that fails here:09:30
markos        setvl 0,0,17,0,1,109:30
markos        sv.ld 10.v, 0(5.v)09:30
markosand this gets translated to:09:30
markos        .long 0x58002180 #      setvl 0,0,17,0,1,109:30
markos        sv.ld 10.v, 0(5.v)09:30
markoswhich obviously fails09:30
markossomething in the parser?09:31
programmerjakeah, it expects one line per list element, not several instructions in one list element09:31
programmerjake    lst = [... (full message at https://libera.ems.host/_matrix/media/r0/download/libera.chat/6f0edaaa6f9b177c11d941818fd41f20fb082e24)09:31
programmerjakegives `['.loop1:', '.long 0x58002180', '.long 0x5403500', 'ld 2, 0(1)']`09:32
programmerjakehopefully that fixes it for you markos09:34
markosthe message was cropped, due to matrix09:34
programmerjakek, i'll re-paste it as smaller sections...09:35
programmerjakelst = [09:35
programmerjake    '.loop1:',09:35
programmerjake    'setvl 0,0,17,0,1,1',09:35
programmerjake    'sv.ld 10.v, 0(5.v)'09:35
markosok, I see, that means it can translate the instruction, but why not inside the original asm source?09:36
programmerjakeall i can think of is you might have done `["insn1\ninsn2\ninsn3"]` rather than `["insn1","insn2","insn3"]`09:37
programmerjakeidk if it affects anything, but SVP64Asm was called with the macros arg:09:38
programmerjake`macros={'win2': '50', 'win': '60'}`09:39
programmerjakeif that doesn't fix it, you'd probably have to ask lkcl09:40
programmerjakeor debug it...09:40
markosok, I'll try to do some debugging, see why it fails09:42
markosI see the op parsed and then it goes into that and it doesn't get translated10:18
markoss/that/that if case/10:19
markosI don't know though why the special casing for len != 2, I'm probably missing the logic here10:20
markosbut the bottom line is that the instruction just gets skipped10:21
markoslkcl, ^ fyi10:24
programmerjakeidk, git blame just leads to https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=ca04665a7b9f54230eb5b8708af9f3e9b446b9f010:25
programmerjake(too bad gitweb has a terrible UI...)10:25
programmerjakemaybe just append a `#` to all your assembly lines? :P10:27
programmerjakeoh, I think i figured out why...10:28
programmerjakeit's so you can have an asm file like:10:28
programmerjake`.long 123, 456 # sv.instr`10:28
programmerjakeeach line would look something like that, allowing it to be assembled by gas without needing to go through SVP64Asm10:29
markoswhat about real comments then?10:48
markosyes, that seemed to work10:48
programmerjakemaybe put them on the line above?10:48
markosok, to comment an sv instruction I have to use double '#'10:49
markosthis seems to work:10:50
markos        setvl 0,0,17,0,1,110:50
markos        # sv.ld 10.v, 0(5.v)10:50
markos#       # sv.fadds/mrr in.v, in.v, in.v10:50
markosit's counter-intuitive though10:51
programmerjakeyeah...it needs to be fixed...10:51
markosie setvl will also not be parsed by gas10:51
markosI'd suggest some other form of annotation, not a plain '#'10:53
lkclmarkos: https://libre-soc.org/irclog/%23libre-soc.2022-03-28.log.html#t2022-03-28T21:09:5110:55
lkclmarkos: we had a nice advert for juniper network devices created on bugzilla, which was the point where trust was eroded and i had to disable account creation10:57
lkclmarkos: you also need to align the vector register numbers to a power of 410:58
markoslkcl, yes, I remember that comment, but it needed something extra apparently10:58
lkclcorrect, setvl will not get parsed by gas, it also has to go through svtrans.py. ghostmansd[m] is working on a new version of binutils gas10:59
markosyou mean, sv.ld 8.v, 0(5.v)?10:59
lkclsv.ld 8.v, 0(4.v)10:59
lkcltry that11:00
markosbut 0(5.v) is just a pointer, why would that need alignment also?11:00
lkcl... i'm half-awake at the moment11:00
markosI get the first11:00
lkclthere's only a certain amount of space to store the "extension" of the SVP64 registers to 12811:01
lkclthere are 5 bits to store the register number in the RA/RB/RC/RT field in the original v3.0B 32-bit opcode11:01
lkcland there are either 2 or 3 bits to store the rest11:02
lkclone of those is "is this a vector or scalar" bit11:02
lkclthat leaves 1 remaining11:02
lkcl2<<6 is not 128, it is 6411:02
lkcltherefore we have to put a zero in the LSB of the Vector Register Number11:02
lkcltherefore, you can only have 0.v 2.v 4.v 6.v 8.v ....11:03
markosyeah, I'm definitely misunderstanding something, what I want is to load 17 (as per the setvl) 'vectors' starting from the memory pointed by register 4, offset 0, to the 'vector' registers starting from 8.v11:04
markosdoes it matter if the address is in register 4 or 5 or whatever?11:05
markosactually I should have mentioned register 5, instead of 4, as that's the input register11:05
lkclyou can't.11:06
lkclit will have to be 4.v as explained above11:06
lkclbut hang on11:06
markosif for some reason it is 5, what will happen? a hardware trap? should that be caught by the assembler?11:07
lkclyou've combined/confused LD-with-immediate with the LD-indexed format11:07
markosyes, I said I'm misunderstanding something :D11:08
lkclyou know the names for the different vector forms?11:08
lkclunit-strided, element-strided, etc?11:09
markosyeah, I admit I didn't read it thoroughly11:10
lkclwhich one do you want? i suspect you want unit-strided11:10
lkcl"memory pointed by register 4" is a scalar11:10
lkcland you want a sequential packed-load from that memory location?11:10
lkclok that's termed "unit-strided"11:11
markosso in the end I think I want sv.ld 8.v, 0(4)11:11
lkclif they're 32-bit you want sv.lwz 8.v, 0(4)11:11
markosok, I was certain I misunderstood something and I was right11:12
lkcljust as in that example.11:12
lkclyou can see at line 88 how it's calculated11:12
lkcl  88         for i in range(VL):11:13
lkcl  89             EA = (RA|0) + EXTS(D) + LDSTsize * i11:13
lkclwhere D-Form is "lwz RT,D(RA)"11:13
lkclbut you have to have RA be a scalar for unit-stride to activate11:14
lkclbasically the problem is that we have to shoe-horn a shed-load of "traditional Vector ISA Modes" on top of a scalar ISA that was never designed with Vectorisation in mind11:15
lkclall without adding any new 32-bit LD/ST instructions11:19
markosok, understood11:21
markoswhat I'm doing right now, is I've modified the C code to only do a few steps at a time and converting the svp64 asm to generate the same output in the same steps11:22
markosin theory, I should be able to match the routine soon, in practice, I'm pretty sure I will hit a corner case where one step will generate the same output, but the next step will be completely different :)11:23
*** alMalsamo is now known as lumberjack12311:42
lkclbtw please do commit what you're doing as you go along11:47
lkclif nobody can see what you're doing, then it's guess-work and i (literally) don't have time to go through that11:48
markoslkcl, of course, but only when I get something worthy commiting, I'm against commiting all my debug steps11:51
lkclmarkos, that's exactly what the basic policy of this project is: to commit all debug steps11:53
lkclplease *don't* "only commit what you consider worthy"11:53
lkclwe are under Audit and Transparency Conditions apart from anything11:53
lkclplus, the "learning" steps - with appropriate commit messages - are just as equally important11:54
lkcl"i made this mistake and here's the change needed to fix it and here's a link to the public discussion which showed what was needed" becomes something that we can use to educate others11:54
lkclso for example, when committing the sv.ld fix you should cross-reference to the IRC channel logs11:55
markoslkcl, that just generates huge git commit logs for no good reason, I have never been in favour of such development processes, I want to be able to read git logs and get the idea behind the actual change, not what was in the coder's mind at the time of development12:01
markosplus it requires extra overhead12:01
lkclmarkos, doesn't matter. this is in part an education project12:01
lkcli do appx 30 commits a day.12:02
lkclit also prevents and prohibits collaboration12:02
markosI do less, but I have 4 projects that I need to work on currently12:02
markosif I had to do that, I would have to work 20h/day12:03
lkclok - then putting the code in with a brief commit message is more important than the explanation12:03
lkclplease: this is really important.12:03
lkclthere are about 6 separate different reasons12:03
lkcl1) if you are unable for any reason to commit then we have lost everything12:04
lkcl2) we are under audit / transparency conditions12:04
lkcl3) nobody else can properly help - we have to "guess" and that takes up my time and everyone else's time12:04
lkcl4) the "learning curve" is lost12:04
lkcl5) other people cannot help you by providing commits12:05
lkcl6) although your time is valuable for you, and it could slow you down, me having to "guess" because i can't see your screen means that overall the project does less because i end up being able to do less12:07
lkcli've a deadline for completing the FPGA of only 2 days remaining.12:07
markos1) I have multiple backups so I'm good there, 2) I know how auditing works, no auditor will care to check each and every print statement, 3) the help part I agree with, but that's what IRC and mails are for, 4) that, plus docs, 5) I wouldn't ask other people to commit stuff on my behalf12:07
lkclplease, markos, this is important.12:08
lkclauditors are not going to look at this12:09
markosI also have 3 contracts running, I also have deadlines for my other projects, I have agreed to work on this not because of financial reasons, but because I really find it fascinating and I think it will be a very important technological evolution in CPU architectures in the next 5 years12:10
lkclwe have a basic and fundamental principle of trust12:10
markosI have committed myself to working on this and learning how this will work12:10
lkcli need to walk away from the keyboard, i am in distress.12:11
markosbut you also have to allow me to work my own way12:11
markosI am not just going to drop a multi-MB commit12:11
markosbut otoh, I cannot commit each and every print statement12:12
lkclsorry about that. i appreciate the help you can give.12:18
markosI don't think we disagree in essence, I *will* give detailed commits and explain all that is done, so people *will* actually be able to follow the code12:19
lkcllet's go over it tonight.12:19
lkclwhich hm i am going to float the idea of moving it hr earlier (to 21:00 UTC)12:20
lkclbecause otherwise it is a mad time for you12:20
markosyes please12:20
markossleeping at 2am because of coding I don't mind, but because of meetings... :-D12:21
tplatenI had a look at external_core_top.v:28258717:45
tplaten(* src = "nmutil/src/nmutil/iocontrol.py:97" *)17:45
tplaten  input spr1__wen;17:45
tplaten  (* syn_ramstyle = "block_ram" *)17:45
tplaten  reg [63:0] memory [23:0];17:45
tplaten  initial begin17:45
tplaten    memory[0] = 64'h0000000000000000;17:45
tplatenAm I using the wrong version of nmutil?17:46
tplatenIn the last few weeks I was only working on microwatt, so I did not update any python packages. My current nmutil version is about one month old.17:50
lkcltplaten, https://git.libre-soc.org/?p=nmutil.git;a=tree18:02
lkcllatest commit is this https://git.libre-soc.org/?p=nmutil.git;a=commit;h=2ef87c06d25b692ede35aa6340a108ba410b440a18:02
lkclalthough there's not been a lot of commits so you should be fine18:03
lkcltplaten: http://lists.libre-soc.org/pipermail/libre-soc-dev/2022-March/004644.html18:03
tplatenI had a look at both nmutil and the last link. All software versions are correct. Upgrading nmutil did not resolve anything18:06
lkclincluding verilator?18:07
lkclwhere *exactly* is the error?18:07
lkclwhich program is reporting an error?18:07
tplatenThe error is on yosys, before verilator is invoked18:08
lkcl"13. Executing Verilog backend" i cannot tell what is reporting that18:08
tplatenwrite_verilog in yosys18:08
lkclwhich commit are you on for nmigen?18:09
lkclit should be this18:09
tplaten$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"18:09
lkclwhich commit for *nmigen*?18:10
lkclthat's "re-importing"18:10
lkclthat's *re-importing* the nmigen-generated verilog file comprising external_core_top.v18:10
lkclwhich was *generated* by nmigen18:10
tplatencommit 37b7d9a9a78fa48042391bf62245a24c2e4d55dc18:10
tplatenAuthor: Luke Kenneth Casson Leighton <lkcl@lkcl.net>18:10
tplatenDate:   Thu Mar 24 13:41:27 2022 +000018:10
tplaten    nextpnr-xilinx can cope with the various IBUF/OBUFs,18:10
tplaten    no need to fall back to standard platform Instance("$tristate") etc.18:10
lkclok great18:10
lkcllet me check18:10
tplatencommit 37b7d9a9a78fa48042391bf62245a24c2e4d55dc18:11
lkclgot it18:11
lkcl1 sec just checking18:11
lkcl2. Executing Verilog backend.18:12
lkclDumping module `\clock_generator_50000000_50000000'.18:12
lkclnot getting any problem here with the microwatt_verilator branch18:13
lkclplease can you check that specific branch18:13
tplatenI'll check that again, last week it was working18:14
tplatenHow does dropping in an external_core work with verilator18:14
tplatenmaybe one change in my branch broke everything18:15
lkclok i get the exact same eror18:15
lkcltherefore you've broken something in the porting18:15
tplatenI agree, most likely I have misunderstood something18:16
tplatenmicrowatt.v: $(synth_files) $(RAM_INIT_FILE)18:16
tplaten 242         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"18:16
lkcllet me take a look18:16
tplatenthis is the make rule in the verilator_trace branch18:17
lkclbasically you musn't try to actually do the BRAM "memory" in verilog/vhdl/nmigen but instead let the verilator c++ do it18:17
tplatenI understand18:18
lkclupstream microwatt tries to convert hexadecimal files into "RAM_INIT_FILE"18:18
lkcltakes RAM_INIT_FILE and turns it into a sequence of registers18:18
lkcli replaced that with a c++ *emulation* of a RAM.18:18
tplatenDoes verilator read the external_core_top.v file,18:19
lkclthat could then be "pre-populated" with the contents of the file to be executed18:19
lkclyes it has to18:19
tplatenI saw that c++ *emulation* of a RAM.18:19
lkcl$ make -n microwatt-verilator18:19
lkclyosys -m ghdl.so -p "ghdl --std=08 --no-formal -gMEMORY_SIZE=536870912 -gRAM_INIT_FILE=dtbImage.microwatt.hex -gRESET_LOW=true -gCLK_INPUT=50000000 -gCLK_FREQUENCY=50000000 -gSIM_MAIN_BRAM=false -gSIM_BRAM_CHAINBOOT=6291456  -gEXTERNAL_CORE=true  decode_types.vhdl common.vhdl wishbone_types.vhdl utils.vhdl core_dummy.vhdl fpga/soc_reset.vhdl fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl nonrandom.vhdl wishbone_arbiter.vhdl18:19
lkclwishbone_bram_wrapper.vhdl sync_fifo.vhdl wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl spi_rxtx.vhdl spi_flash_ctrl.vhdl fpga/clk_gen_bypass.vhd fpga/top-generic.vhdl dmi_dtm_dummy.vhdl -e toplevel; write_verilog microwatt.v"18:19
lkclthat's in the microwatt-verilator branch18:20
lkcl$ make -n microwatt-verilator18:20
lkclyosys -m ghdl -p "ghdl --std=08 --no-formal -gMEMORY_SIZE=8192 -gRAM_INIT_FILE=hello_world/hello_world.hex -gRESET_LOW=true -gCLK_INPUT=50000000 -gCLK_FREQUENCY=50000000 -gICACHE_NUM_LINES=4  decode_types.vhdl common.vhdl wishbone_types.vhdl utils.vhdl core_dummy.vhdl helpers.vhdl gpio.vhdl cache_ram.vhdl   fpga/soc_reset.vhdl fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl nonrandom.vhdl wishbone_arbiter.vhdl wishbone_bram_wrapper.vh18:20
lkcldl sync_fifo.vhdl wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl spi_rxtx.vhdl spi_flash_ctrl.vhdl plru_dummy.vhdl fpga/clk_gen_bypass.vhd fpga/top-generic.vhdl dmi_dtm_dummy.vhdl -e toplevel; read_verilog uart16550/raminfr.v uart16550/uart_defines.v uart16550/uart_receiver.v uart16550/uart_regs.v uart16550/uart_rfifo.v uart16550/uart_sync_flops.v uart16550/uart_tfifo.v uart16550/uart_top.v uart16550/uart_transmitter.v18:20
lkcluart16550/uart_wb.v external_core_top.v; write_verilog microwatt.v"18:20
lkclthat's in your branch18:20
lkclyou're missing:18:21
lkcl* -gSIM_MAIN_BRAM=false18:21
lkcl* -gSIM_BRAM_CHAINBOOT (which is only needed for linux-5.7 dtbImage so that's ok)18:21
lkcl* having the uart16550 instead of potato is [probably] ok18:22
lkcland you have also added external_core_top.v18:25
lkclwhich i believe verilator will pick up automatically through its "includes" system18:27
tplatenI first check if the verilator version is correct, undo the adding of external_core_top.v, then retry18:28
lkclbasically you musn't randomly add things that "appear to be missing"18:28
lkclfor example -Iuart16550 \ in the Makefile on the microwatt-verilator target18:29
lkclthat says to verilator, "if you encounter an object named uart_16550 then when you are performing the hunting in *.v files looking for it please also search the uart16550 subdirectory as well"18:30
lkclexactly like #includes for c/c++18:30
lkcltherefore if you explicitly added the uart16550/*.v files (because you thought "hm these are missing i'll add them") i suggest removing them18:31
tplatenSome time ago when I tried to install verilator v4.106, I got weird errors such as error: 'cerr' is not a member of 'std' where I gave up and used apt-get install verilator18:38
tplatenThat gave me a version that is too old.18:38
tplatenI was able to build all other packages that I need.18:38
lkcldid you build it from a debian/10 schroot?18:38
tplatenyes I did18:40
lkclthat's very odd18:42
tplatenOn the host system I can install verilator, I have all other tools in schroots, including one for coriolis218:51
lkclthis is on amd64 or ppc64le?18:51
tplatenWhile compiling verilator I was reading on crowdsupply.com18:55
tplatenI saw that a HyperRAM controller is used for USB analysis in LUNA.18:56
tplatenI assume 32 MBytes of HyperRAM is barely enough for a small linux. I knew that Linus Torwalds had 4 MBytes when he wrote linux (from his book).19:01
tplatenBuild completed, now running make test19:03
lkclyes it's just about manageable.  openwrt linux kernels and the OSes typically fit into 16 mbytes. just19:03
lkcli actually have 2 of them and there are 4x PMOD ports (2 per HyperRAM) so if absolutely necessary i can put the 2nd one onto the Arty A719:05
tplatenTests passed!19:08
lkclexcellent. that's a verilator build?19:09
tplatenYes, verilator. I ran make test before make install19:10
tplatenIn verilator_trace I did a grep: microwatt.v:  external_core_top \processor_external.processor  (20:21
tplatenthis is clearly missing in my branch20:21
lkcli had to add it to soc.vhdl20:25
lkcllkcl@fizzy:~/src/libresoc/microwatt-orangecrab$ grep external_core *.vhdl20:26
lkcllkcl@fizzy:~/src/libresoc/microwatt2$ grep external_core *.vhdl20:26
lkclsoc.vhdl:    component external_core_top port (20:26
lkclsoc.vhdl:       processor: external_core_top20:26
lkclit's a bit of a pain: you also need to add a "dummy" version so that when compiling EXTERNAL_CORE=false for microwatt it can go "ok i found an external_core instance"20:27
lkclwhich *later* it goes "hey that's not needed... now i can delete it"20:27
tplatenI found out already out, I have a dummy version20:27
* lkcl thinks20:30
lkcl    processor_external: if EXTERNAL_CORE generate20:30
lkcl    processor: external_core_top20:31
lkcl25 lines above that, if putting something similar20:31
lkclprocessor_internal: if NOT EXTERNAL_CORE generate20:31
lkcl    processor: entity work.core20:31
lkcli think that might do away with the need for creating core_dummy.vhdl20:31
markoslkcl, so, is the meeting at 21UTC?20:46
markosapparently not...21:04
lkcl22:00 UTC :)21:06
lkclwhich is... errr... i make that 2 hours from now. 1h54m21:06
lkclBST... err...21:07
markoscrap, DST21:07
lkclsigh yes21:07
markosthat's going to be 1am here21:07
lkclhence discussing moving it 1hr earlier from next week21:07
markosI don't think I will make it this time, it's just too late21:07
markosso I'll just mention some progress here21:08
lkclno problem, will discuss about moving earlier21:08
lkcloh, sure, great21:08
markosso I've done -at least I think I have- the first for loop in SVP6421:09
markosand I'm writing a tiny test program to compare the result, the actual mp3_1_test actually compares to the data files and I'm a long way from that21:09
markosbut I am monitoring the simulator and I see that the lwz, fadds/mrr and the stw (that I'm doing afterwards to store the resulting buffer for comparison) are executing exactly 17 times as  per the setvl21:10
* lkcl thinks21:11
markosI have no reason to expect wrong results from such trivial instructions, but I will write the tiny test tomorrow and will grow on that21:11
lkclperhaps the mp3_1_test (with c-converted-to-assembler) would be a way to confirm, first21:11
markossince you care about the educational aspect of this, I was planning to suggest that I commit this part in steps21:11
markosbut I know this one already passes the test21:11
lkclthen do incremental changes converting to svp64?21:11
lkclahh :)21:12
markosthat's what I'll do21:12
lkclyes please21:12
lkclthe commit messages don't need to be massive / detailed.21:12
markosI will convert the svp64 in parts, but I will have to partially disable the respective parts of the C code, and compare21:12
markosno, but they have to be explanatory21:12
lkcltrue :)21:12
lkclohh i see. actually take out the corresponding parts in the original c algorithm and compare that way?21:13
markosyes exactly21:13
lkclahh neat. like it21:13
markosit will also help me understand the incremental process of porting to SVP6421:13
markosI would never hope to convert in one single pass :D21:14
markosnow that I at least figured out how to make this work, I can make gradual progress21:14
markoseven a couple of lines per day will do21:14
lkclif you need to, feel free to add to any of the svp64 unit tests21:14
markosyes, that's a good idea21:14
lkclwith even just 1 instruction, input registers/memory, and "expected results"21:15
markosI will ask you for commit access one of these days21:15
lkcli do that all the time21:15
lkclyeah that would help :)21:15
markosquite :)21:15
markosok, I'm going to call it a night, I'm beat, the past days I've been waking super early and sleeping very late, I would stay for the meeting if it was now-ish, but I can't wait 2 hours :)21:16
lkclyehh totally understand21:16
lkcltill next time21:17
programmerjakelkcl: so the meeting hasn't been moved for today?21:48
octaviusIs the meeting at 22:00UTC?21:53
octaviusoops XD21:53
programmerjakeafaict it's in 1hr5min21:55
programmerjakei'm assuming lkcl will move it next week if it gets moved21:55
octaviusAh ok, thanks21:57
lkcl10m or so22:47
lkclcesar, lx0 jn octavius programmerjake toshywoshy22:47
lkclbut i'm on now22:47
lkclif i can find the right URL that is22:47
programmerjakedefinitely shouldn't have stayed up till 5am ... i'll be there in a few min22:51

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