Load Byte and Zero

D-Form

• lbz RT,D(RA)

Pseudo-code:

b <- (RA|0)
EA <- b + EXTS(D)
RT <- [0]*56 || MEM(EA, 1)

Special Registers Altered:

None

Load Byte and Zero Indexed

X-Form

• lbzx RT,RA,RB

Pseudo-code:

b <- (RA|0)
EA <- b + (RB)
RT <- [0] * 56 || MEM(EA, 1)

Special Registers Altered:

None

Load Byte and Zero with Update

D-Form

• lbzu RT,D(RA)

Pseudo-code:

EA <- (RA) + EXTS(D)
RT <- [0] * 56 || MEM(EA, 1)
RA <- EA

Special Registers Altered:

None

Load Byte and Zero with Update Indexed

X-Form

• lbzux RT,RA,RB

Pseudo-code:

EA <- (RA) + (RB)
RT <- [0] * 56 || MEM(EA, 1)
RA <- EA

Special Registers Altered:

None

Load Halfword and Zero

D-Form

• lhz RT,D(RA)

Pseudo-code:

b <- (RA|0)
EA <- b + EXTS(D)
RT <- [0] * 48 || MEM(EA, 2)

Special Registers Altered:

None

Load Halfword and Zero Indexed

X-Form

• lhzx RT,RA,RB

Pseudo-code:

b <- (RA|0)
EA <- b + (RB)
RT <- [0] * 48 || MEM(EA, 2)

Special Registers Altered:

None

Load Halfword and Zero with Update

D-Form

• lhzu RT,D(RA)

Pseudo-code:

EA <- (RA) + EXTS(D)
RT <- [0] * 48 || MEM(EA, 2)
RA <- EA

Special Registers Altered:

None

Load Halfword and Zero with Update Indexed

X-Form

• lhzux RT,RA,RB

Pseudo-code:

EA <- (RA) + (RB)
RT <- [0] * 48 || MEM(EA, 2)
RA <- EA

Special Registers Altered:

None

Load Halfword Algebraic

D-Form

• lha RT,D(RA)

Pseudo-code:

b <- (RA|0)
EA <- b + EXTS(D)
RT <- EXTS(MEM(EA, 2))

Special Registers Altered:

None

Load Halfword Algebraic Indexed

X-Form

• lhax RT,RA,RB

Pseudo-code:

b <- (RA|0)
EA <- b + (RB)
RT <- EXTS(MEM(EA, 2))

Special Registers Altered:

None

Load Halfword Algebraic with Update

D-Form

• lhau RT,D(RA)

Pseudo-code:

EA <- (RA) + EXTS(D)
RT <- EXTS(MEM(EA, 2))
RA <- EA

Special Registers Altered:

None

Load Halfword Algebraic with Update Indexed

X-Form

• lhaux RT,RA,RB

Pseudo-code:

EA <- (RA) + (RB)
RT <- EXTS(MEM(EA, 2))
RA <- EA

Special Registers Altered:

None

Load Word and Zero

D-Form

• lwz RT,D(RA)

Pseudo-code:

b <- (RA|0)
EA <- b + EXTS(D)
RT <- [0] * 32 || MEM(EA, 4)

Special Registers Altered:

None

Load Word and Zero Indexed

X-Form

• lwzx RT,RA,RB

Pseudo-code:

b <- (RA|0)
EA <- b + (RB)
RT <- [0] * 32 || MEM(EA, 4)

Special Registers Altered:

None

Load Word and Zero with Update

D-Form

• lwzu RT,D(RA)

Pseudo-code:

EA <- (RA) + EXTS(D)
RT <- [0]*32 || MEM(EA, 4)
RA <- EA

Special Registers Altered:

None

Load Word and Zero with Update Indexed

X-Form

• lwzux RT,RA,RB

Pseudo-code:

EA <- (RA) + (RB)
RT <- [0] * 32 || MEM(EA, 4)
RA <- EA

Special Registers Altered:

None

Load Word Algebraic

D-Form

• lwa RT,DS(RA)

Pseudo-code:

b <- (RA|0)
EA <- b + EXTS(DS || 0b00)
RT <- EXTS(MEM(EA, 4))

Special Registers Altered:

None

Load Word Algebraic Indexed

X-Form

• lwax RT,RA,RB

Pseudo-code:

b <- (RA|0)
EA <- b + (RB)
RT <- EXTS(MEM(EA, 4))

Special Registers Altered:

None

Load Word Algebraic with Update Indexed

X-Form

• lwaux RT,RA,RB

Pseudo-code:

EA <- (RA) + (RB)
RT <- EXTS(MEM(EA, 4))
RA <- EA

Special Registers Altered:

None

Load Doubleword

DS-Form

• ld RT,DS(RA)

Pseudo-code:

b <- (RA|0)
EA <- b + EXTS(DS || 0b00)
RT <- MEM(EA, 8)

Special Registers Altered:

None

Load Doubleword Indexed

X-Form

• ldx RT,RA,RB

Pseudo-code:

b <- (RA|0)
EA <- b + (RB)
RT <- MEM(EA, 8)

Special Registers Altered:

None

Load Doubleword with Update Indexed

DS-Form

• ldu RT,DS(RA)

Pseudo-code:

EA <- (RA) + EXTS(DS || 0b00)
RT <- MEM(EA, 8)
RA <- EA

Special Registers Altered:

None

Load Doubleword with Update Indexed

X-Form

• ldux RT,RA,RB

Pseudo-code:

EA <- (RA) + (RB)
RT <- MEM(EA, 8)
RA <- EA

Special Registers Altered:

None

Load Quadword

DQ-Form

• lq RTp,DQ(RA)

Pseudo-code:

b <- (RA|0)
EA <- b + EXTS(DQ || 0b0000)
RTp <- MEM(EA, 16)

Special Registers Altered:

None

Load Halfword Byte-Reverse Indexed

X-Form

• lhbrx RT,RA,RB

Pseudo-code:

b <- (RA|0)
EA <- b + (RB)
load_data <- MEM(EA, 2)
RT <- [0]*48 || load_data[8:15] || load_data[0:7]

Special Registers Altered:

None

Load Word Byte-Reverse Indexed

X-Form

• lwbrx RT,RA,RB

Pseudo-code:

b <- (RA|0)
EA <- b + (RB)
load_data <- MEM(EA, 4)
RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
                || load_data[8:15]  || load_data[0:7])

Special Registers Altered:

None

Load Doubleword Byte-Reverse Indexed

X-Form

• ldbrx RT,RA,RB

Pseudo-code:

b <- (RA|0)
EA <- b + (RB)
load_data <- MEM(EA, 8)
RT <- (load_data[56:63] || load_data[48:55]
    || load_data[40:47] || load_data[32:39]
    || load_data[24:31] || load_data[16:23]
    || load_data[8:15]  || load_data[0:7])

Special Registers Altered:

None

Load Multiple Word

DQ-Form

• lmw RT,D(RA)

Pseudo-code:

b <- (RA|0)
EA <- b + EXTS(D)
r <- RT
do while r <=  31
    GPR(r) <- [0]*32 || MEM(EA, 4)
    r <- r + 1
    EA <- EA + 4

Special Registers Altered:

None