Links

• About HiTAS: https://www-soc.lip6.fr/equipe-cian/logiciels/tasyagle/
• Bug: https://bugs.libre-soc.org/show_bug.cgi?id=890
• Source: https://gitlab.lip6.fr/vlsi-eda/tas-yagle
• Coriolis2 installation: coriolis2
• HDL workflow: HDL workflow
• Devscript: https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=tasyagle-install;hb=HEAD

HiTAS -- Static Timing Analyser

"HiTas is a static timing analysis tool. Its strength lies in its transparent hierarchical approach combined with the ability to perform analysis at the transistor-level, cell-level or a mixture of the two." - Copied from the website linked above

Installation instructions

NOTE: These are required to setup a new chroot, copy over the devscript repo, and make sure the new chroot has all the necessary packages.

1. ./mk-deb-chroot tasyagle
2. ./cp-scripts-to-chroot tasyagle

3. (tasyagle) ./install-hdl-apt-reqs

4. (tasyagle) ./tasyagle-install

The binaries are installed to /usr/local/bin

Run "xtas" to launch the GUI for the timing analyzer.

Documentation

The documentation for HiTAS and Yagle is extensive, and is compiled by the "tasyagle-install" script. You'll find the HTML and PDF documents under these directories:

• distrib/docxml2/compiled/dochtml
• distrib/docxml2/compiled/docpdf

The tutorial files are located here:

• distrib/share/tutorials

Tutorials

NOTE: The AVERTEC_TOP and PATH variables must be loaded using "source ~/.bashrc" before trying run these examples!

The tutorial files are located in the following directories:

• distrib/share/tutorials/hitas
• distrib/share/tutorials/yagle
• distrib/share/tutorials/yagle_gns

One of the basic examples, a CMOS inverter, located under 'hitas/inv', shows the setup tcl script 'db.tcl' and SPICE file defining the inverter 'inv.spi'.

To run the inverter example, cd into the 'inv' directory and run:

• ./db.tcl

NOTE: Currently running the tutorials results in:

"[Fatal Internal Error AVT-027]: Internal error, please contact Avertec support"