Documentation
A draft version of the specification is available at https://ftp.libre-soc.org/power-spec-draft.pdf
Codebase Structure
The SOC is partitioned into four repositories. The subrepositories are intended as general purpose standalone projects useful outside of LibreSOC. For example, the IEE754 FPU repository is a general purpose IEEE754 toolkit for the construction of FSMs and arbitrary length pipelines.
| Git Repo | Online docs | Description | Pypi |
|---|---|---|---|
| SOC | Libre-SOC | Main OpenPOWER Hybrid CPU-GPU | TBD |
| FPU | ieee754fpu | Equivalent to hardfloat-3 | libresoc-ieee754fpu |
| nmutil | nmutil | Equivalent to Chisel3.util | libresoc-nmutil |
| OpenPOWER ISA | OpenPOWER ISA | Simulator, ISA spec compiler, co-simulation infrastructure | libresoc-openpower-isa |
Installing the Codebase
Installation is much easier when using the install scripts. A separate script also helps install dependencies and a third can be used to set up a debootstrap chroot. The chroot is useful to ensure stability and repeatable builds: no errors or issues introduced by libraries being wrong versions. Also relevant is the gdb gcc build.
For a simple set of commands to follow, see devscripts. If you prefer to do a manual install and explicitly install dependencies yourself, in order to verify them, see HDL workflow
Tutorials and documentation
- SOC Architecture
- Gtkwave Tutorial gtkwave tutorial
- Formal proof notes notes on formal proofs
- Learning nmigen learning nmigen
- Test API testapi
- Pinmux and JTAG Boundary Scan pinmux
- pypowersim python-based command-line simulator pypowersim
- First steps firststeps
- Adding an instruction adding instr - see also below
SVP64
Currently in Draft form, svp64 is the basis of the Supercomputing Cray-style Vectorisation of the Power ISA.
Checklist for adding an instruction
TODO. use the commit diffs for these instructions as a guide
- fmvis https://bugs.libre-soc.org/show_bug.cgi?id=887
- avgadd etc. https://bugs.libre-soc.org/show_bug.cgi?id=863
- int min/max https://bugs.libre-soc.org/show_bug.cgi?id=234#c1
- ternlogi https://bugs.libre-soc.org/show_bug.cgi?id=745 which included adding a hardware implementation as well