Luke Kenneth Casson Leighton
Lead dev and Project Coordinator for Libre-SOC.
Status tracking
move things along from one stage to the next
Currently working on
- Project Management
- https://bugs.libre-soc.org/show_bug.cgi?id=609 SVSTATE DMI
- https://bugs.libre-soc.org/show_bug.cgi?id=588 SVP64 PowerDecoder2
- https://bugs.libre-soc.org/show_bug.cgi?id=575
- https://bugs.libre-soc.org/show_bug.cgi?id=53 3D Custom instructions
- https://bugs.libre-soc.org/show_bug.cgi?id=565 Partitioning Proof
- https://bugs.libre-soc.org/show_bug.cgi?id=557 AV Opcode documrntation
- EUR
- https://bugs.libre-soc.org/show_bug.cgi?id=546 Data merging FSM
- EUR
- https://bugs.libre-soc.org/show_bug.cgi?id=556 SV Overview
- https://bugs.libre-soc.org/show_bug.cgi?id=213 SV Spec
- https://bugs.libre-soc.org/show_bug.cgi?id=214 ISAMux writeup
- https://bugs.libre-soc.org/show_bug.cgi?id=202 HDL changes for coriolis2
- https://bugs.libre-soc.org/show_bug.cgi?id=425
- https://bugs.libre-soc.org/show_bug.cgi?id=466 3D MESA planning
- https://bugs.libre-soc.org/show_bug.cgi?id=432
- https://bugs.libre-soc.org/show_bug.cgi?id=450
- https://bugs.libre-soc.org/show_bug.cgi?id=458 PartitionedSignal Module
- http://bugs.libre-riscv.org/show_bug.cgi?id=81 6600 scoreboard
- http://bugs.libre-riscv.org/show_bug.cgi?id=206 branch prediction research
- https://bugs.libre-soc.org/show_bug.cgi?id=216 LDST buffer
- https://bugs.libre-soc.org/show_bug.cgi?id=448 MUL tests
- shared with cole
- https://bugs.libre-soc.org/show_bug.cgi?id=419 MUL proof
- EUR 50, shared with samuel 10%
- https://bugs.libre-soc.org/show_bug.cgi?id=420 DIV proof
- https://bugs.libre-soc.org/show_bug.cgi?id=340 SHIFTROT proof
- https://bugs.libre-soc.org/show_bug.cgi?id=336 Compunit RA=0 test
- https://bugs.libre-soc.org/show_bug.cgi?id=418 SPR proof
- EUR 50, shared with samuel (EUR 350)
- https://bugs.libre-soc.org/show_bug.cgi?id=350 LDST RA=0 test
- https://bugs.libre-soc.org/show_bug.cgi?id=361 RA=0 tests
- https://bugs.libre-soc.org/show_bug.cgi?id=415 misc opcodes
- https://bugs.libre-soc.org/show_bug.cgi?id=310 FU multiple tasks
- https://bugs.libre-soc.org/show_bug.cgi?id=482 mul bug
- https://bugs.libre-soc.org/show_bug.cgi?id=427 LD/ST cache-inhibit
- EUR 200
- https://bugs.libre-soc.org/show_bug.cgi?id=490 litex peripheral set
- https://bugs.libre-soc.org/show_bug.cgi?id=514 ls180 reset review
- https://bugs.libre-soc.org/show_bug.cgi?id=515 JTAG boot upload/init
- https://bugs.libre-soc.org/show_bug.cgi?id=511 JTAG IO Boundary test
- https://bugs.libre-soc.org/show_bug.cgi?id=64 data handling API
- https://bugs.libre-soc.org/show_bug.cgi?id=211 Formal proof of decoder
- donated
- parent #198
- EUR 200
- https://bugs.libre-soc.org/show_bug.cgi?id=342 parent #197
- MultiCompUnit (and Function Units) proof
- https://bugs.libre-soc.org/show_bug.cgi?id=340 POWER9 ROTATE proof
- donated
- parent #195
Completed but not yet submitted:
- https://bugs.libre-soc.org/show_bug.cgi?id=606 PowerDecoder2 simplification
- https://bugs.libre-soc.org/show_bug.cgi?id=519 ULX3S boot
- Project 2019-10-043 06dec2020 wishbone
- EUR 0 (TBD)
Project 2019-10-029 14mar2020 coriolis2
- https://bugs.libre-soc.org/show_bug.cgi?id=508 pin-package for 180nm ASIC
- (total EUR 100 shared 50% with staf)
- EUR 50 lkcl
- https://bugs.libre-soc.org/show_bug.cgi?id=507 ls180 ioring and pads
- (total EUR 1500 shared 50% with LIP6)
- EUR 750 lkcl
- https://bugs.libre-soc.org/show_bug.cgi?id=521 multi-clock example
- (total EUR 400 shared 75% with LIP6)
- EUR 300 lkcl
Project 2019-02-012 06dec2020 Core
- https://bugs.libre-soc.org/show_bug.cgi?id=538 pipeline API continued
- EUR 700 lkcl, EUR 500 programmerjake, total EUR 1200
- http://bugs.libre-riscv.org/show_bug.cgi?id=208 CORDIC
- EUR 750 donated
- https://bugs.libre-soc.org/show_bug.cgi?id=94 LDST Dep Matrix
- EUR 1500
Project 2019-10-043 06dec2020 wishbone
- https://bugs.libre-soc.org/show_bug.cgi?id=348 SPR pipe
- EUR 250 lkcl, EUR 50 programmerjake, total EUR 300
- https://bugs.libre-soc.org/show_bug.cgi?id=416 DEC/TB
- EUR 200
- https://bugs.libre-soc.org/show_bug.cgi?id=426 LD/ST sign-extend
- EUR 100
- https://bugs.libre-soc.org/show_bug.cgi?id=468 wishbone downconverter
- EUR 200
- https://bugs.libre-soc.org/show_bug.cgi?id=349 privileged detection
- EUR 100
- https://bugs.libre-soc.org/show_bug.cgi?id=478 mfcr FXM
- EUR 200
- https://bugs.libre-soc.org/show_bug.cgi?id=407 XICS
- EUR 450
- https://bugs.libre-soc.org/show_bug.cgi?id=476 addme bug
- EUR 100
- http://bugs.libre-riscv.org/show_bug.cgi?id=186 POWER Decoder
- EUR 200 donated
- https://bugs.libre-soc.org/show_bug.cgi?id=493 DMI to JTAG
- EUR 250 (share with cole)
Project 2019-10-032 06dec2020 proofs
- https://bugs.libre-soc.org/show_bug.cgi?id=306 POWER9 ALU proof
- parent #195
- EUR 400 donated
- https://bugs.libre-soc.org/show_bug.cgi?id=332 POWER9 CR proof
- parent #195
- EUR 300 donated
- https://bugs.libre-soc.org/show_bug.cgi?id=335 POWER9 BRANCH proof
- EUR 400 donated
- parent #195
- https://bugs.libre-soc.org/show_bug.cgi?id=331 POWER9 LOGICAL proof
- EUR 400 donated
- parent #195
Submitted for NLNet RFP
submitted but not confirmed paid:
Project 2019-02-012 04sep2020 Core
- https://bugs.libre-soc.org/show_bug.cgi?id=412 litex
- EUR 2000 total, shared with florent. EUR 1200
Project 2019-02-012 Date {TEMPLATE INSERT DATE}
Paid
donation from NLNet confirmed received:
2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
- https://bugs.libre-soc.org/show_bug.cgi?id=463
- EUR 2000, python POWER9 simulator
- Shared 50% with mnolan, EUR 1000
- https://bugs.libre-soc.org/show_bug.cgi?id=272
- EUR 250, functions needed for simulator
- Shared 20% with mnolan, EUR 50
proofs 2019-10-032
- https://bugs.libre-soc.org/show_bug.cgi?id=421 Trap proof
- EUR 500 shared 20% samuel, EUR 100
- https://bugs.libre-soc.org/show_bug.cgi?id=332 CR proof
- EUR 300 shared 1/6 mnolan EUR 50
- https://bugs.libre-soc.org/show_bug.cgi?id=331 Logic proof
- EUR 400 shared 25% mnolan EUR 100
- https://bugs.libre-soc.org/show_bug.cgi?id=312 countzero proof
- EUR 150
wishbone 2019-10-043
- https://bugs.libre-soc.org/show_bug.cgi?id=460 Document 6600
- EUR 500
- https://bugs.libre-soc.org/show_bug.cgi?id=393 WB to LDST
- EUR 300
- https://bugs.libre-soc.org/show_bug.cgi?id=414 DMI interface
- EUR 250
- http://bugs.libre-riscv.org/show_bug.cgi?id=186 opcode decoder
- EUR 500, shared 40%, with mnolan (40%), programmerjake (20%), EUR 200
- https://bugs.libre-soc.org/show_bug.cgi?id=339 SHIFTROT pipe
- EUR 300
- https://bugs.libre-soc.org/show_bug.cgi?id=441 test improvement
- EUR 400, 50% shared programmerjake EUR 200
- https://bugs.libre-soc.org/show_bug.cgi?id=323 MUL pipe
- EUR 750, 33% shared programmerjake EUR 250
- https://bugs.libre-soc.org/show_bug.cgi?id=351 virtual regfile port
- EUR 200 50% shared, cole, EUR 100
- https://bugs.libre-soc.org/show_bug.cgi?id=345 POWER9 regfiles
- EUR 200
- https://bugs.libre-soc.org/show_bug.cgi?id=325 Trap pipe
- EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
- https://bugs.libre-soc.org/show_bug.cgi?id=382 SRAM wishbone object
- EUR 150
- https://bugs.libre-soc.org/show_bug.cgi?id=305 ALU pipe
- EUR 400 shared 50% mnolan EUR 200
- https://bugs.libre-soc.org/show_bug.cgi?id=313 Branch pipe
- EUR 250 shared 40% mnolan EUR 100
- https://bugs.libre-soc.org/show_bug.cgi?id=314 CR pipe
- EUR 300 shared 1/3 mnolan EUR 100
- https://bugs.libre-soc.org/show_bug.cgi?id=330 Logic pipe
- EUR 300 shared 50% mnolan EUR 150
- https://bugs.libre-soc.org/show_bug.cgi?id=346 regfile-core
- EUR 750
- https://bugs.libre-soc.org/show_bug.cgi?id=344 add mtmsrd
- EUR 100
- https://bugs.libre-soc.org/show_bug.cgi?id=409 illegal instructions
- EUR 100
- https://bugs.libre-soc.org/show_bug.cgi?id=435 MSR and PC "state"
- EUR 100
- https://bugs.libre-soc.org/show_bug.cgi?id=324 DIV pipe
- EUR 1500 shared with programmerjake 1/3 (EUR 500)
Project 2019-02-012 28-apr-2020
- https://bugs.libre-soc.org/show_bug.cgi?id=292
- 6600 scoreboard multi-read/write
- EUR 600
- http://bugs.libre-riscv.org/show_bug.cgi?id=171 parent #48
- Partitioned equals and greater than comparison
- Shared 50% with mnolan
- EUR 200 (each)
- http://bugs.libre-riscv.org/show_bug.cgi?id=173 parent #48
- partitioned scalar/vector shift
- Shared 50% with lkcl
- EUR 350 (each)
2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
- https://bugs.libre-soc.org/show_bug.cgi?id=269 parent #241
- auto-parser of POWER9
- Shared 50% with mnolan
- EUR 500 (each)
Project 2019-10-029 Date 14mar2020
- http://bugs.libre-riscv.org/show_bug.cgi?id=178 coriolis2 start/tutorial
- EUR 1200
Project 2019-02-012 Date 12mar2020
- http://bugs.libre-riscv.org/show_bug.cgi?id=113 fcvt range 100% EUR 250
- http://bugs.libre-riscv.org/show_bug.cgi?id=171 50% with mnolan EUR 200
- http://bugs.libre-riscv.org/show_bug.cgi?id=173 dynamic shift 50% with mnolan EUR 350
- http://bugs.libre-riscv.org/show_bug.cgi?id=127 EUR 900 shared with programmerjake
Project 2019-02-012 Date 28jan2020
- admin tasks
- http://bugs.libre-riscv.org/show_bug.cgi?id=147