Store Byte
D-Form
- stb RS,D(RA)
Pseudo-code:
b <- (RA|0)
EA <- b + EXTS(D)
MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
Description:
Let the effective address (EA) be the sum (RA|0)+ D.
RS[56:63] are stored into the byte in storage addressed
by EA.
Special Registers Altered:
None
Store Byte Indexed
X-Form
- stbx RS,RA,RB
Pseudo-code:
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
Description:
Let the effective address (EA) be the sum
(RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
age addressed by EA.
Special Registers Altered:
None
Store Byte with Update
D-Form
- stbu RS,D(RA)
Pseudo-code:
EA <- (RA) + EXTS(D)
MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
RA <- EA
Description:
Let the effective address (EA) be the sum (RA)+ D.
RS[56:63] are stored into the byte in storage addressed
by EA.
EA is placed into register RA.
If RA=0, the instruction form is invalid.
Special Registers Altered:
None
Store Byte with Update Indexed
X-Form
- stbux RS,RA,RB
Pseudo-code:
EA <- (RA) + (RB)
MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
RA <- EA
Description:
Let the effective address (EA) be the sum (RA)+ (RB).
RS[56:63] are stored into the byte in storage addressed
by EA.
EA is placed into register RA.
If RA=0, the instruction form is invalid.
Special Registers Altered:
None
Store Halfword
D-Form
- sth RS,D(RA)
Pseudo-code:
b <- (RA|0)
EA <- b + EXTS(D)
MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
Description:
Let the effective address (EA) be the sum (RA|0)+ D.
RS[48:63] are stored into the halfword in storage
addressed by EA.
Special Registers Altered:
None
Store Halfword Indexed
X-Form
- sthx RS,RA,RB
Pseudo-code:
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
Description:
Let the effective address (EA) be the sum
(RA|0)+ (RB). RS[48:63] are stored into the halfword in
storage addressed by EA.
Special Registers Altered:
None
Store Halfword with Update
D-Form
- sthu RS,D(RA)
Pseudo-code:
EA <- (RA) + EXTS(D)
MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
RA <- EA
Description:
Let the effective address (EA) be the sum (RA)+ D.
RS[48:63] are stored into the halfword in storage
addressed by EA.
EA is placed into register RA.
If RA=0, the instruction form is invalid.
Special Registers Altered:
None
Store Halfword with Update Indexed
X-Form
- sthux RS,RA,RB
Pseudo-code:
EA <- (RA) + (RB)
MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
RA <- EA
Description:
Let the effective address (EA) be the sum (RA)+ (RB).
RS[48:63] are stored into the halfword in storage
addressed by EA.
EA is placed into register RA.
If RA=0, the instruction form is invalid.
Special Registers Altered:
None
Store Word
D-Form
- stw RS,D(RA)
Pseudo-code:
b <- (RA|0)
EA <- b + EXTS(D)
MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
Description:
Let the effective address (EA) be the sum (RA|0)+ D.
RS[32:63] are stored into the word in storage addressed
by EA.
Special Registers Altered:
None
Store Word Indexed
X-Form
- stwx RS,RA,RB
Pseudo-code:
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
Description:
Let the effective address (EA) be the sum
(RA|0)+ (RB). RS[32:63] are stored into the word in stor-
age addressed by EA.
Special Registers Altered:
None
Store Word with Update
D-Form
- stwu RS,D(RA)
Pseudo-code:
EA <- (RA) + EXTS(D)
MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
RA <- EA
Description:
Let the effective address (EA) be the sum (RA)+ D.
RS[32:63] are stored into the word in storage addressed
by EA.
EA is placed into register RA.
If RA=0, the instruction form is invalid.
Special Registers Altered:
None
Store Word with Update Indexed
X-Form
- stwux RS,RA,RB
Pseudo-code:
EA <- (RA) + (RB)
MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
RA <- EA
Description:
Let the effective address (EA) be the sum (RA)+ (RB).
RS[32:63] are stored into the word in storage addressed
by EA.
EA is placed into register RA.
If RA=0, the instruction form is invalid.
Special Registers Altered:
None
Store Doubleword
DS-Form
- std RS,DS(RA)
Pseudo-code:
b <- (RA|0)
EA <- b + EXTS(DS || 0b00)
MEM(EA, 8) <- (RS)
Description:
Let the effective address (EA) be the sum
(RA|0)+ (DS||0b00). (RS) is stored into the doubleword
in storage addressed by EA.
Special Registers Altered:
None
Store Doubleword Indexed
X-Form
- stdx RS,RA,RB
Pseudo-code:
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 8) <- (RS)
Description:
Let the effective address (EA) be the sum
(RA|0)+ (RB). (RS) is stored into the doubleword in
storage addressed by EA.
Special Registers Altered:
None
Store Doubleword with Update
DS-Form
- stdu RS,DS(RA)
Pseudo-code:
EA <- (RA) + EXTS(DS || 0b00)
MEM(EA, 8) <- (RS)
RA <- EA
Description:
Let the effective address (EA) be the sum
(RA)+ (DS||0b00). (RS) is stored into the doubleword in
storage addressed by EA.
EA is placed into register RA.
If RA=0, the instruction form is invalid.
Special Registers Altered:
None
Store Doubleword with Update Indexed
X-Form
- stdux RS,RA,RB
Pseudo-code:
EA <- (RA) + (RB)
MEM(EA, 8) <- (RS)
RA <- EA
Description:
Let the effective address (EA) be the sum (RA)+ (RB).
(RS) is stored into the doubleword in storage
addressed by EA.
EA is placed into register RA.
If RA=0, the instruction form is invalid.
Special Registers Altered:
None
Store Quadword
DS-Form
- stq RSp,DS(RA)
Pseudo-code:
b <- (RA|0)
EA <- b + EXTS(DS || 0b00)
MEM(EA, 16) <- RSp
Description:
Let the effective address (EA) be the sum (RA|0)+
(DS||0b00). The contents of register pair RSp are
stored into the quadword in storage addressed by EA.
If RSp is odd, the instruction form is invalid.
The contents of an even-odd pair of GPRs is stored into
the quadword in storage addressed by EA as follows.
In Big-Endian mode, the even-numbered GPR is stored
into the doubleword in storage addressed by EA and
the odd-numbered GPR is stored into the doubleword
addressed by EA+8. In Little-Endian mode, the
even-numbered GPR is stored byte-reversed into the
doubleword in storage addressed by EA+8 and the
odd-numbered GPR is stored byte-reversed into the
doubleword addressed by EA.
Special Registers Altered:
None
Store Halfword Byte-Reverse Indexed
X-Form
- sthbrx RS,RA,RB
Pseudo-code:
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
Description:
Let the effective address (EA) be the sum
(RA|0)+ (RB). (RS)56:63 are stored into bits 0:7 of the
halfword in storage addressed by EA. (RS) 48:55 are
stored into bits 8:15 of the halfword in storage
addressed by EA.
Special Registers Altered:
None
Store Word Byte-Reverse Indexed
X-Form
- stwbrx RS,RA,RB
Pseudo-code:
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
||(RS)[32:39])
Description:
Let the effective address (EA) be the sum
(RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
word in storage addressed by EA. (RS) [48:55] are stored
into bits 8:15 of the word in storage addressed by EA.
(RS)[40:47] are stored into bits 16:23 of the word in stor-
age addressed by EA. (RS) [32:39] are stored into bits
24:31 of the word in storage addressed by EA.
Special Registers Altered:
None
Store Doubleword Byte-Reverse Indexed
X-Form
- stdbrx RS,RA,RB
Pseudo-code:
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
|| (RS)[40:47] || (RS)[32:39]
|| (RS)[24:31] || (RS)[16:23]
|| (RS)[8:15] || (RS)[0:7])
Description:
Let the effective address (EA) be the sum
(RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
doubleword in storage addressed by EA. (RS) [48:55] are
stored into bits 8:15 of the doubleword in storage
addressed by EA. (RS) [40:47] are stored into bits 16:23 of
the doubleword in storage addressed by EA. (RS) [32:39]
are stored into bits 23:31 of the doubleword in storage
addressed by EA. (RS) [24:31] are stored into bits 32:39 of
the doubleword in storage addressed by EA. (RS) [16:23]
are stored into bits 40:47 of the doubleword in storage
addressed by EA. (RS)[8:15] are stored into bits 48:55 of
the doubleword in storage addressed by EA. (RS) [0:7]
are stored into bits 56:63 of the doubleword in storage
addressed by EA.
Special Registers Altered:
None
Store Multiple Word
D-Form
- stmw RS,D(RA)
Pseudo-code:
b <- (RA|0)
EA <- b + EXTS(D)
r <- RS[0:63]
do while r <= 31
MEM(EA, 4) <- GPR(r)[32:63]
r <- r + 1
EA <- EA + 4
Description:
Let n = (32-RS). Let the effective address (EA) be the
sum (RA|0)+ D.
n consecutive words starting at EA are stored from the
low-order 32 bits of GPRs RS through 31.
This instruction is not supported in Little-Endian mode.
If it is executed in Little-Endian mode, the system align-
ment error handler is invoked.
Special Registers Altered:
None