Load Byte and Zero with Post-Update

D-Form

• lbzup RT,D(RA)

Pseudo-code:

EA <- (RA)
RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
RA <- (RA) + EXTS(D)

Special Registers Altered:

None

Load Byte and Zero with Post-Update Indexed

X-Form

• lbzupx RT,RA,RB

Pseudo-code:

EA <- (RA)
RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
RA <- (RA) + (RB)

Special Registers Altered:

None

Load Halfword and Zero with Post-Update

D-Form

• lhzup RT,D(RA)

Pseudo-code:

EA <- (RA)
RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
RA <- (RA) + EXTS(D)

Special Registers Altered:

None

Load Halfword and Zero with Post-Update Indexed

X-Form

• lhzupx RT,RA,RB

Pseudo-code:

EA <- (RA)
RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
RA <- (RA) + (RB)

Special Registers Altered:

None

Load Halfword Algebraic with Post-Update

D-Form

• lhaup RT,D(RA)

Pseudo-code:

EA <- (RA)
RT <- EXTS(MEM(EA, 2))
RA <- (RA) + EXTS(D)

Special Registers Altered:

None

Load Halfword Algebraic with Post-Update Indexed

X-Form

• lhaupx RT,RA,RB

Pseudo-code:

EA <- (RA)
RT <- EXTS(MEM(EA, 2))
RA <- (RA) + (RB)

Special Registers Altered:

None

Load Word and Zero with Post-Update

D-Form

• lwzup RT,D(RA)

Pseudo-code:

EA <- (RA)
RT <- [0]*32 || MEM(EA, 4)
RA <- (RA) + EXTS(D)

Special Registers Altered:

None

Load Word and Zero with Post-Update Indexed

X-Form

• lwzupx RT,RA,RB

Pseudo-code:

EA <- (RA)
RT <- [0] * 32 || MEM(EA, 4)
RA <- (RA) + (RB)

Special Registers Altered:

None

Load Word Algebraic with Post-Update Indexed

X-Form

• lwaupx RT,RA,RB

Pseudo-code:

EA <- (RA)
RT <- EXTS(MEM(EA, 4))
RA <- (RA) + (RB)

Special Registers Altered:

None

Load Doubleword with Post-Update Indexed

DS-Form

• ldup RT,DS(RA)

Pseudo-code:

EA <- (RA)
RT <- MEM(EA, 8)
RA <- (RA) + EXTS(DS || 0b00)

Special Registers Altered:

None

Load Doubleword with Post-Update Indexed

X-Form

• ldupx RT,RA,RB

Pseudo-code:

EA <- (RA)
RT <- MEM(EA, 8)
RA <- (RA) + (RB)

Special Registers Altered:

None