Store Byte with Post-Update Indexed Shifted
Z23-Form
- stbupsx RS,RA,RB,SH
Pseudo-code:
EA <- (RA) + (RB)<<(SH+1)
ea <- (RA)
MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
RA <- EA
Description:
Let the effective address (EA) be the sum of the contents of
register RB shifted by (SH+1), and the contents of register RA.
(RS)[56:63] are stored into the byte in storage addressed by EA.
EA is placed into register RA.
If RA=0, the instruction form is invalid.
Special Registers Altered:
None
Store Halfword with Post-Update Indexed Shifted
Z23-Form
- sthupsx RS,RA,RB,SH
Pseudo-code:
EA <- (RA) + (RB)<<(SH+1)
ea <- (RA)
MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
RA <- EA
Description:
Let the effective address (EA) be the sum of the contents of
register RB shifted by (SH+1), and the contents of register RA.
(RS)[56:63] are stored into the byte in storage addressed by EA.
EA is placed into register RA.
If RA=0, the instruction form is invalid
Special Registers Altered:
None
Store Word with Post-Update Indexed Shifted
Z23-Form
- stwupsx RS,RA,RB,SH
Pseudo-code:
EA <- (RA) + (RB)<<(SH+1)
ea <- (RA)
MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
RA <- EA
Description:
Let the effective address (EA) be the sum of the contents of
register RB shifted by (SH+1), and the contents of register RA.
(RS)[32:63] are stored into the word in storage addressed by RA.
EA is placed into register RA.
If RA=0, the instruction form is invalid.
Special Registers Altered:
None
Store Doubleword with Post-Update Indexed Shifted
Z23-Form
- stdupsx RS,RA,RB,SH
Pseudo-code:
EA <- (RA) + (RB)<<(SH+1)
ea <- (RA)
MEM(ea, 8) <- (RS)
RA <- EA
Description:
Let the effective address (EA) be the sum of the contents of
register RB shifted by (SH+1), and the contents of register RA.
(RS) is stored into the doubleword in storage addressed by RA.
EA is placed into register RA.
If RA=0, the instruction form is invalid.
Special Registers Altered:
None