[DRAFT] Floating Add FFT/DCT [Single]

A-Form

• ffadds FRT,FRA,FRB (Rc=0)
• ffadds. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPADD32(FRA, FRB)
FRS <- FPSUB32(FRB, FRA)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

[DRAFT] Floating Add FFT/DCT [Double]

A-Form

• ffadd FRT,FRA,FRB (Rc=0)
• ffadd. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPADD64(FRA, FRB)
FRS <- FPSUB64(FRB, FRA)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

[DRAFT] Floating Subtract FFT/DCT [Single]

A-Form

• ffsubs FRT,FRA,FRB (Rc=0)
• ffsubs. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPSUB32(FRB, FRA)
FRS <- FPADD32(FRA, FRB)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

[DRAFT] Floating Subtract FFT/DCT [Double]

A-Form

• ffsub FRT,FRA,FRB (Rc=0)
• ffsub. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPSUB64(FRB, FRA)
FRS <- FPADD64(FRA, FRB)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

[DRAFT] Floating Multiply FFT/DCT [Single]

A-Form

• ffmuls FRT,FRA,FRC (Rc=0)
• ffmuls. FRT,FRA,FRC (Rc=1)

Pseudo-code:

FRT <- FPMUL32(FRA, FRC)
FRS <- FPMUL32(FRA, FRC, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

[DRAFT] Floating Multiply FFT/DCT [Double]

A-Form

• ffmul FRT,FRA,FRC (Rc=0)
• ffmul. FRT,FRA,FRC (Rc=1)

Pseudo-code:

FRT <- FPMUL64(FRA, FRC)
FRS <- FPMUL64(FRA, FRC, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

[DRAFT] Floating Divide FFT/DCT [Single]

A-Form

• ffdivs FRT,FRA,FRB (Rc=0)
• ffdivs. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPDIV32(FRA, FRB)
FRS <- FPDIV32(FRA, FRB, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

[DRAFT] Floating Divide FFT/DCT [Double]

A-Form

• ffdiv FRT,FRA,FRB (Rc=0)
• ffdiv. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPDIV64(FRA, FRB)
FRS <- FPDIV64(FRA, FRB, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

[DRAFT] Floating Twin Multiply-Add DCT [Single]

DCT-Form

• fdmadds FRT,FRA,FRB (Rc=0)
• fdmadds. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRS <- FPADD32(FRT, FRB)
sub <- FPSUB32(FRT, FRB)
FRT <- FPMUL32(FRA, sub)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)

[DRAFT] Floating Multiply-Add FFT [Single]

A-Form

• ffmadds FRT,FRA,FRB (Rc=0)
• ffmadds. FRT,FRA,FRB (Rc=1)

Pseudo-code:

tmp <- FRT
FRT <- FPMULADD32(tmp, FRA, FRB, 1, 1)
FRS <- FPMULADD32(tmp, FRA, FRB, -1, 1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)

[DRAFT] Floating Multiply-Sub FFT [Single]

A-Form

• ffmsubs FRT,FRA,FRB (Rc=0)
• ffmsubs. FRT,FRA,FRB (Rc=1)

Pseudo-code:

tmp <- FRT
FRT <- FPMULADD32(tmp, FRA, FRB, 1, -1)
FRS <- FPMULADD32(tmp, FRA, FRB, -1, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)

[DRAFT] Floating Negative Multiply-Add FFT [Single]

A-Form

• ffnmadds FRT,FRA,FRB (Rc=0)
• ffnmadds. FRT,FRA,FRB (Rc=1)

Pseudo-code:

tmp <- FRT
FRT <- FPMULADD32(tmp, FRA, FRB, -1, -1)
FRS <- FPMULADD32(tmp, FRA, FRB, 1, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)

[DRAFT] Floating Negative Multiply-Sub FFT [Single]

A-Form

• ffnmsubs FRT,FRA,FRB (Rc=0)
• ffnmsubs. FRT,FRA,FRB (Rc=1)

Pseudo-code:

tmp <- FRT
FRT <- FPMULADD32(tmp, FRA, FRB, -1, 1)
FRS <- FPMULADD32(tmp, FRA, FRB, 1, 1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)