effect of more decode stages on reg renaming

there's basically no effect except execution starts a few cycles later. no additional execution resources are needed, notice the exact same number of renamed hardware registers are used.

5 decode stages, 4 wide

Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0x100: mtctr r4 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: mtctr h2 \<- h1 Read Inputs: h1 Write Outputs: h2 Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: ldu h3, 8(h0 -> h4) Read Inputs: h0 Write Outputs: h3, h4 Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: addi h5 \<- h3, 100 Wait: h3 Read Inputs: h3 Write Outputs: h5 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: std h5, 0(h4) Wait: h5, h4 Wait: h5 Read Inputs: h5, h4 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: bdnz h6 \<- h2, .L2 Read Inputs: h2 Write Outputs: h6 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: ldu h7, 8(h4 -> h8) Wait: all execution pipes busy Read Inputs: h4 Write Outputs: h7, h8 Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: addi h9 \<- h7, 100 Wait: h7 Wait: h7 Read Inputs: h7 Write Outputs: h9 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: std h9, 0(h8) Wait: h9, h8 Wait: h9, h8 Wait: h9 Read Inputs: h9, h8 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: bdnz h10 \<- h6, .L2 Read Inputs: h6 Write Outputs: h10 Wait: Retire Wait: Retire Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: ldu h11, 8(h8 -> h12) Wait: h8 Read Inputs: h8 Write Outputs: h11, h12 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: addi h13 \<- h11, 100 Wait: h11 Wait: h11 Read Inputs: h11 Write Outputs: h13 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: std h13, 0(h12) Wait: h13, h12 Wait: h13, h12 Wait: h13 Read Inputs: h13, h12 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: bdnz h14 \<- h10, .L2 Read Inputs: h10 Write Outputs: h14 Wait: Retire Wait: Retire Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: ldu h15, 8(h12 -> h16) Wait: h12 Wait: all execution pipes busy Wait: all execution pipes busy Read Inputs: h12 Write Outputs: h15, h16 Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: addi h17 \<- h15, 100 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Read Inputs: h15 Write Outputs: h17 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: std h17, 0(h16) Wait: h17, h16 Wait: h17, h16 Wait: h17, h16 Wait: h17, h16 Wait: h17 Read Inputs: h17, h16 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: bdnz h18 \<- h14, .L2 Read Inputs: h14 Write Outputs: h18 Wait: Retire Wait: Retire Wait: Retire Wait: Retire Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: ldu h19, 8(h16 -> h20) Wait: h16 Wait: h16 Wait: h16 Read Inputs: h16 Write Outputs: h19, h20 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: addi h21 \<- h19, 100 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Read Inputs: h19 Write Outputs: h21 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: std h21, 0(h20) Wait: h21, h20 Wait: h21, h20 Wait: h21, h20 Wait: h21, h20 Wait: h21 Read Inputs: h21, h20 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: bdnz h22 \<- h18, .L2 Read Inputs: h18 Write Outputs: h22 Wait: Retire Wait: Retire Wait: Retire Wait: Retire Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: ldu h23, 8(h20 -> h24) Wait: h20 Wait: h20 Wait: h20 Wait: all execution pipes busy Wait: all execution pipes busy Read Inputs: h20 Write Outputs: h23, h24 Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: addi h25 \<- h23, 100 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Read Inputs: h23 Write Outputs: h25 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: std h25, 0(h24) Wait: h25, h24 Wait: h25, h24 Wait: h25, h24 Wait: h25, h24 Wait: h25, h24 Wait: h25, h24 Wait: h25 Read Inputs: h25, h24 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Renamed: bdnz h26 \<- h22, .L2 Read Inputs: h22 Write Outputs: h26 Wait: Retire Wait: Retire Wait: Retire Wait: Retire Wait: Retire Wait: Retire Wait: Retire Retire

1 decode stage, 4 wide

Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0x100: mtctr r4 Fetch Decode 0 Renamed: mtctr h2 \<- h1 Read Inputs: h1 Write Outputs: h2 Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Renamed: ldu h3, 8(h0 -> h4) Read Inputs: h0 Write Outputs: h3, h4 Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Renamed: addi h5 \<- h3, 100 Wait: h3 Read Inputs: h3 Write Outputs: h5 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Renamed: std h5, 0(h4) Wait: h5, h4 Wait: h5 Read Inputs: h5, h4 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Renamed: bdnz h6 \<- h2, .L2 Read Inputs: h2 Write Outputs: h6 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Renamed: ldu h7, 8(h4 -> h8) Wait: all execution pipes busy Read Inputs: h4 Write Outputs: h7, h8 Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Renamed: addi h9 \<- h7, 100 Wait: h7 Wait: h7 Read Inputs: h7 Write Outputs: h9 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Renamed: std h9, 0(h8) Wait: h9, h8 Wait: h9, h8 Wait: h9 Read Inputs: h9, h8 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Renamed: bdnz h10 \<- h6, .L2 Read Inputs: h6 Write Outputs: h10 Wait: Retire Wait: Retire Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Renamed: ldu h11, 8(h8 -> h12) Wait: h8 Read Inputs: h8 Write Outputs: h11, h12 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Renamed: addi h13 \<- h11, 100 Wait: h11 Wait: h11 Read Inputs: h11 Write Outputs: h13 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Renamed: std h13, 0(h12) Wait: h13, h12 Wait: h13, h12 Wait: h13 Read Inputs: h13, h12 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Renamed: bdnz h14 \<- h10, .L2 Read Inputs: h10 Write Outputs: h14 Wait: Retire Wait: Retire Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Renamed: ldu h15, 8(h12 -> h16) Wait: h12 Wait: all execution pipes busy Wait: all execution pipes busy Read Inputs: h12 Write Outputs: h15, h16 Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Renamed: addi h17 \<- h15, 100 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Read Inputs: h15 Write Outputs: h17 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Renamed: std h17, 0(h16) Wait: h17, h16 Wait: h17, h16 Wait: h17, h16 Wait: h17, h16 Wait: h17 Read Inputs: h17, h16 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Renamed: bdnz h18 \<- h14, .L2 Read Inputs: h14 Write Outputs: h18 Wait: Retire Wait: Retire Wait: Retire Wait: Retire Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Renamed: ldu h19, 8(h16 -> h20) Wait: h16 Wait: h16 Wait: h16 Read Inputs: h16 Write Outputs: h19, h20 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Renamed: addi h21 \<- h19, 100 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Read Inputs: h19 Write Outputs: h21 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Renamed: std h21, 0(h20) Wait: h21, h20 Wait: h21, h20 Wait: h21, h20 Wait: h21, h20 Wait: h21 Read Inputs: h21, h20 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Renamed: bdnz h22 \<- h18, .L2 Read Inputs: h18 Write Outputs: h22 Wait: Retire Wait: Retire Wait: Retire Wait: Retire Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 0 Renamed: ldu h23, 8(h20 -> h24) Wait: h20 Wait: h20 Wait: h20 Wait: all execution pipes busy Wait: all execution pipes busy Read Inputs: h20 Write Outputs: h23, h24 Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 0 Renamed: addi h25 \<- h23, 100 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Read Inputs: h23 Write Outputs: h25 Retire
0x10c: std r9, 0(r3) Fetch Decode 0 Renamed: std h25, 0(h24) Wait: h25, h24 Wait: h25, h24 Wait: h25, h24 Wait: h25, h24 Wait: h25, h24 Wait: h25, h24 Wait: h25 Read Inputs: h25, h24 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 0 Renamed: bdnz h26 \<- h22, .L2 Read Inputs: h22 Write Outputs: h26 Wait: Retire Wait: Retire Wait: Retire Wait: Retire Wait: Retire Wait: Retire Wait: Retire Retire

8 decode stages, 8 wide

Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0x100: mtctr r4 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: mtctr h2 \<- h1 Read Inputs: h1 Write Outputs: h2 Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: ldu h3, 8(h0 -> h4) Read Inputs: h0 Write Outputs: h3, h4 Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: addi h5 \<- h3, 100 Wait: h3 Read Inputs: h3 Write Outputs: h5 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: std h5, 0(h4) Wait: h5, h4 Wait: h5 Read Inputs: h5, h4 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: bdnz h6 \<- h2, .L2 Wait: h2 Read Inputs: h2 Write Outputs: h6 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: ldu h7, 8(h4 -> h8) Wait: h4 Read Inputs: h4 Write Outputs: h7, h8 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: addi h9 \<- h7, 100 Wait: h7 Wait: h7 Read Inputs: h7 Write Outputs: h9 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: std h9, 0(h8) Wait: h9, h8 Wait: h9, h8 Wait: h9 Read Inputs: h9, h8 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: bdnz h10 \<- h6, .L2 Wait: h6 Read Inputs: h6 Write Outputs: h10 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: ldu h11, 8(h8 -> h12) Wait: h8 Read Inputs: h8 Write Outputs: h11, h12 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: addi h13 \<- h11, 100 Wait: h11 Wait: h11 Read Inputs: h11 Write Outputs: h13 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: std h13, 0(h12) Wait: h13, h12 Wait: h13, h12 Wait: h13 Read Inputs: h13, h12 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: bdnz h14 \<- h10, .L2 Wait: h10 Wait: h10 Read Inputs: h10 Write Outputs: h14 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: ldu h15, 8(h12 -> h16) Wait: h12 Read Inputs: h12 Write Outputs: h15, h16 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: addi h17 \<- h15, 100 Wait: h15 Wait: h15 Read Inputs: h15 Write Outputs: h17 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: std h17, 0(h16) Wait: h17, h16 Wait: h17, h16 Wait: h17 Read Inputs: h17, h16 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: bdnz h18 \<- h14, .L2 Wait: h14 Wait: h14 Read Inputs: h14 Write Outputs: h18 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: ldu h19, 8(h16 -> h20) Wait: h16 Wait: h16 Read Inputs: h16 Write Outputs: h19, h20 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: addi h21 \<- h19, 100 Wait: h19 Wait: h19 Wait: h19 Read Inputs: h19 Write Outputs: h21 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: std h21, 0(h20) Wait: h21, h20 Wait: h21, h20 Wait: h21, h20 Wait: h21 Read Inputs: h21, h20 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: bdnz h22 \<- h18, .L2 Wait: h18 Wait: h18 Wait: h18 Read Inputs: h18 Write Outputs: h22 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: ldu h23, 8(h20 -> h24) Wait: h20 Wait: h20 Read Inputs: h20 Write Outputs: h23, h24 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: addi h25 \<- h23, 100 Wait: h23 Wait: h23 Wait: h23 Read Inputs: h23 Write Outputs: h25 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: std h25, 0(h24) Wait: h25, h24 Wait: h25, h24 Wait: h25, h24 Wait: h25 Read Inputs: h25, h24 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Decode 8 Renamed: bdnz h26 \<- h22, .L2 Wait: h22 Wait: h22 Wait: h22 Read Inputs: h22 Write Outputs: h26 Wait: Retire Retire

1 decode stage, 8 wide

Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0x100: mtctr r4 Fetch Decode 1 Renamed: mtctr h2 \<- h1 Read Inputs: h1 Write Outputs: h2 Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Renamed: ldu h3, 8(h0 -> h4) Read Inputs: h0 Write Outputs: h3, h4 Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Renamed: addi h5 \<- h3, 100 Wait: h3 Read Inputs: h3 Write Outputs: h5 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Renamed: std h5, 0(h4) Wait: h5, h4 Wait: h5 Read Inputs: h5, h4 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Renamed: bdnz h6 \<- h2, .L2 Wait: h2 Read Inputs: h2 Write Outputs: h6 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Renamed: ldu h7, 8(h4 -> h8) Wait: h4 Read Inputs: h4 Write Outputs: h7, h8 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Renamed: addi h9 \<- h7, 100 Wait: h7 Wait: h7 Read Inputs: h7 Write Outputs: h9 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Renamed: std h9, 0(h8) Wait: h9, h8 Wait: h9, h8 Wait: h9 Read Inputs: h9, h8 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Renamed: bdnz h10 \<- h6, .L2 Wait: h6 Read Inputs: h6 Write Outputs: h10 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Renamed: ldu h11, 8(h8 -> h12) Wait: h8 Read Inputs: h8 Write Outputs: h11, h12 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Renamed: addi h13 \<- h11, 100 Wait: h11 Wait: h11 Read Inputs: h11 Write Outputs: h13 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Renamed: std h13, 0(h12) Wait: h13, h12 Wait: h13, h12 Wait: h13 Read Inputs: h13, h12 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Renamed: bdnz h14 \<- h10, .L2 Wait: h10 Wait: h10 Read Inputs: h10 Write Outputs: h14 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Renamed: ldu h15, 8(h12 -> h16) Wait: h12 Read Inputs: h12 Write Outputs: h15, h16 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Renamed: addi h17 \<- h15, 100 Wait: h15 Wait: h15 Read Inputs: h15 Write Outputs: h17 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Renamed: std h17, 0(h16) Wait: h17, h16 Wait: h17, h16 Wait: h17 Read Inputs: h17, h16 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Renamed: bdnz h18 \<- h14, .L2 Wait: h14 Wait: h14 Read Inputs: h14 Write Outputs: h18 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Renamed: ldu h19, 8(h16 -> h20) Wait: h16 Wait: h16 Read Inputs: h16 Write Outputs: h19, h20 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Renamed: addi h21 \<- h19, 100 Wait: h19 Wait: h19 Wait: h19 Read Inputs: h19 Write Outputs: h21 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Renamed: std h21, 0(h20) Wait: h21, h20 Wait: h21, h20 Wait: h21, h20 Wait: h21 Read Inputs: h21, h20 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Renamed: bdnz h22 \<- h18, .L2 Wait: h18 Wait: h18 Wait: h18 Read Inputs: h18 Write Outputs: h22 Wait: Retire Retire
0x104: ldu r9, 8(r3) Fetch Decode 1 Renamed: ldu h23, 8(h20 -> h24) Wait: h20 Wait: h20 Read Inputs: h20 Write Outputs: h23, h24 Wait: Retire Retire
0x108: addi r9 \<- r9, 100 Fetch Decode 1 Renamed: addi h25 \<- h23, 100 Wait: h23 Wait: h23 Wait: h23 Read Inputs: h23 Write Outputs: h25 Retire
0x10c: std r9, 0(r3) Fetch Decode 1 Renamed: std h25, 0(h24) Wait: h25, h24 Wait: h25, h24 Wait: h25, h24 Wait: h25 Read Inputs: h25, h24 Write Outputs: Retire
0x110: bdnz .L2 Fetch Decode 1 Renamed: bdnz h26 \<- h22, .L2 Wait: h22 Wait: h22 Wait: h22 Read Inputs: h22 Write Outputs: h26 Wait: Retire Retire

simple loop, 1 decode stage, 8 wide

Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h1 \<- h0, -1 Read Inputs: h0 Write Outputs: h1 Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h2 \<- h1, 0 Wait: h1 Read Inputs: h1 Write Outputs: h2 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h2, .L2 Wait: h2 Wait: h2 Read Inputs: h2 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h3 \<- h1, -1 Wait: h1 Read Inputs: h1 Write Outputs: h3 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h4 \<- h3, 0 Wait: h3 Wait: h3 Read Inputs: h3 Write Outputs: h4 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h4, .L2 Wait: h4 Wait: h4 Wait: h4 Read Inputs: h4 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h5 \<- h3, -1 Wait: h3 Wait: h3 Read Inputs: h3 Write Outputs: h5 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h6 \<- h5, 0 Wait: h5 Wait: h5 Wait: h5 Read Inputs: h5 Write Outputs: h6 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h6, .L2 Wait: h6 Wait: h6 Wait: h6 Read Inputs: h6 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h7 \<- h5, -1 Wait: h5 Wait: h5 Read Inputs: h5 Write Outputs: h7 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h8 \<- h7, 0 Wait: h7 Wait: h7 Wait: h7 Read Inputs: h7 Write Outputs: h8 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h8, .L2 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Read Inputs: h8 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h9 \<- h7, -1 Wait: h7 Wait: h7 Wait: h7 Read Inputs: h7 Write Outputs: h9 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h10 \<- h9, 0 Wait: h9 Wait: h9 Wait: h9 Wait: h9 Read Inputs: h9 Write Outputs: h10 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h10, .L2 Wait: h10 Wait: h10 Wait: h10 Wait: h10 Wait: h10 Read Inputs: h10 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h11 \<- h9, -1 Wait: h9 Wait: h9 Wait: h9 Wait: h9 Read Inputs: h9 Write Outputs: h11 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h12 \<- h11, 0 Wait: h11 Wait: h11 Wait: h11 Wait: h11 Read Inputs: h11 Write Outputs: h12 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h12, .L2 Wait: h12 Wait: h12 Wait: h12 Wait: h12 Wait: h12 Read Inputs: h12 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h13 \<- h11, -1 Wait: h11 Wait: h11 Wait: h11 Wait: h11 Read Inputs: h11 Write Outputs: h13 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h14 \<- h13, 0 Wait: h13 Wait: h13 Wait: h13 Wait: h13 Wait: h13 Read Inputs: h13 Write Outputs: h14 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h14, .L2 Wait: h14 Wait: h14 Wait: h14 Wait: h14 Wait: h14 Wait: h14 Read Inputs: h14 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h15 \<- h13, -1 Wait: h13 Wait: h13 Wait: h13 Wait: h13 Wait: h13 Read Inputs: h13 Write Outputs: h15 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h16 \<- h15, 0 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Read Inputs: h15 Write Outputs: h16 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h16, .L2 Wait: h16 Wait: h16 Wait: h16 Wait: h16 Wait: h16 Wait: h16 Wait: h16 Read Inputs: h16 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h17 \<- h15, -1 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Read Inputs: h15 Write Outputs: h17 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h18 \<- h17, 0 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Read Inputs: h17 Write Outputs: h18 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h18, .L2 Wait: h18 Wait: h18 Wait: h18 Wait: h18 Wait: h18 Wait: h18 Wait: h18 Read Inputs: h18 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h19 \<- h17, -1 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Read Inputs: h17 Write Outputs: h19 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h20 \<- h19, 0 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Read Inputs: h19 Write Outputs: h20 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h20, .L2 Wait: h20 Wait: h20 Wait: h20 Wait: h20 Wait: h20 Wait: h20 Wait: h20 Wait: h20 Read Inputs: h20 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h21 \<- h19, -1 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Read Inputs: h19 Write Outputs: h21 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h22 \<- h21, 0 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Read Inputs: h21 Write Outputs: h22 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h22, .L2 Wait: h22 Wait: h22 Wait: h22 Wait: h22 Wait: h22 Wait: h22 Wait: h22 Wait: h22 Read Inputs: h22 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h23 \<- h21, -1 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Read Inputs: h21 Write Outputs: h23 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h24 \<- h23, 0 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Read Inputs: h23 Write Outputs: h24 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h24, .L2 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Read Inputs: h24 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h25 \<- h23, -1 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Read Inputs: h23 Write Outputs: h25 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h26 \<- h25, 0 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Read Inputs: h25 Write Outputs: h26 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h26, .L2 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Read Inputs: h26 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h27 \<- h25, -1 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Read Inputs: h25 Write Outputs: h27 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h28 \<- h27, 0 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Read Inputs: h27 Write Outputs: h28 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h28, .L2 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Read Inputs: h28 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h29 \<- h27, -1 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Read Inputs: h27 Write Outputs: h29 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h30 \<- h29, 0 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Read Inputs: h29 Write Outputs: h30 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h30, .L2 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Read Inputs: h30 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Renamed: addi h31 \<- h29, -1 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Read Inputs: h29 Write Outputs: h31 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Renamed: cmpdi h0 \<- h31, 0 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Read Inputs: h31 Write Outputs: h0 Retire
0x108: bne .L2 Fetch Decode 0 Renamed: bne h0, .L2 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Read Inputs: h0 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Wait: not enough free regs Renamed: addi h2 \<- h31, -1 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Read Inputs: h31 Write Outputs: h2 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Wait: not enough free regs Renamed: cmpdi h1 \<- h2, 0 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Read Inputs: h2 Write Outputs: h1 Retire
0x108: bne .L2 Fetch Decode 0 Wait: not enough free regs Renamed: bne h1, .L2 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Read Inputs: h1 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Wait: not enough free regs Wait: not enough free regs Renamed: addi h4 \<- h2, -1 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Read Inputs: h2 Write Outputs: h4 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Wait: not enough free regs Wait: not enough free regs Renamed: cmpdi h3 \<- h4, 0 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Read Inputs: h4 Write Outputs: h3 Retire
0x108: bne .L2 Fetch Decode 0 Wait: not enough free regs Wait: not enough free regs Renamed: bne h3, .L2 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Read Inputs: h3 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Wait: not enough free regs Wait: not enough free regs Wait: not enough free regs Renamed: addi h6 \<- h4, -1 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Read Inputs: h4 Write Outputs: h6 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Wait: not enough free regs Wait: not enough free regs Wait: not enough free regs Renamed: cmpdi h5 \<- h6, 0 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Read Inputs: h6 Write Outputs: h5 Retire
0x108: bne .L2 Fetch Decode 0 Wait: not enough free regs Wait: not enough free regs Renamed: bne h5, .L2 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Read Inputs: h5 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Wait: not enough free regs Wait: not enough free regs Wait: not enough free regs Renamed: addi h8 \<- h6, -1 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Read Inputs: h6 Write Outputs: h8 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Wait: not enough free regs Wait: not enough free regs Wait: not enough free regs Renamed: cmpdi h7 \<- h8, 0 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Read Inputs: h8 Write Outputs: h7 Retire
0x108: bne .L2 Fetch Decode 0 Wait: not enough free regs Wait: not enough free regs Wait: not enough free regs Renamed: bne h7, .L2 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Read Inputs: h7 Write Outputs: Retire

simple loop, 8 decode stages, 8 wide

Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h1 \<- h0, -1 Read Inputs: h0 Write Outputs: h1 Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h2 \<- h1, 0 Wait: h1 Read Inputs: h1 Write Outputs: h2 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h2, .L2 Wait: h2 Wait: h2 Read Inputs: h2 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h3 \<- h1, -1 Wait: h1 Read Inputs: h1 Write Outputs: h3 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h4 \<- h3, 0 Wait: h3 Wait: h3 Read Inputs: h3 Write Outputs: h4 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h4, .L2 Wait: h4 Wait: h4 Wait: h4 Read Inputs: h4 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h5 \<- h3, -1 Wait: h3 Wait: h3 Read Inputs: h3 Write Outputs: h5 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h6 \<- h5, 0 Wait: h5 Wait: h5 Wait: h5 Read Inputs: h5 Write Outputs: h6 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h6, .L2 Wait: h6 Wait: h6 Wait: h6 Read Inputs: h6 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h7 \<- h5, -1 Wait: h5 Wait: h5 Read Inputs: h5 Write Outputs: h7 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h8 \<- h7, 0 Wait: h7 Wait: h7 Wait: h7 Read Inputs: h7 Write Outputs: h8 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h8, .L2 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Read Inputs: h8 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h9 \<- h7, -1 Wait: h7 Wait: h7 Wait: h7 Read Inputs: h7 Write Outputs: h9 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h10 \<- h9, 0 Wait: h9 Wait: h9 Wait: h9 Wait: h9 Read Inputs: h9 Write Outputs: h10 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h10, .L2 Wait: h10 Wait: h10 Wait: h10 Wait: h10 Wait: h10 Read Inputs: h10 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h11 \<- h9, -1 Wait: h9 Wait: h9 Wait: h9 Wait: h9 Read Inputs: h9 Write Outputs: h11 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h12 \<- h11, 0 Wait: h11 Wait: h11 Wait: h11 Wait: h11 Read Inputs: h11 Write Outputs: h12 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h12, .L2 Wait: h12 Wait: h12 Wait: h12 Wait: h12 Wait: h12 Read Inputs: h12 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h13 \<- h11, -1 Wait: h11 Wait: h11 Wait: h11 Wait: h11 Read Inputs: h11 Write Outputs: h13 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h14 \<- h13, 0 Wait: h13 Wait: h13 Wait: h13 Wait: h13 Wait: h13 Read Inputs: h13 Write Outputs: h14 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h14, .L2 Wait: h14 Wait: h14 Wait: h14 Wait: h14 Wait: h14 Wait: h14 Read Inputs: h14 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h15 \<- h13, -1 Wait: h13 Wait: h13 Wait: h13 Wait: h13 Wait: h13 Read Inputs: h13 Write Outputs: h15 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h16 \<- h15, 0 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Read Inputs: h15 Write Outputs: h16 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h16, .L2 Wait: h16 Wait: h16 Wait: h16 Wait: h16 Wait: h16 Wait: h16 Wait: h16 Read Inputs: h16 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h17 \<- h15, -1 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Wait: h15 Read Inputs: h15 Write Outputs: h17 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h18 \<- h17, 0 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Read Inputs: h17 Write Outputs: h18 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h18, .L2 Wait: h18 Wait: h18 Wait: h18 Wait: h18 Wait: h18 Wait: h18 Wait: h18 Read Inputs: h18 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h19 \<- h17, -1 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Wait: h17 Read Inputs: h17 Write Outputs: h19 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h20 \<- h19, 0 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Read Inputs: h19 Write Outputs: h20 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h20, .L2 Wait: h20 Wait: h20 Wait: h20 Wait: h20 Wait: h20 Wait: h20 Wait: h20 Wait: h20 Read Inputs: h20 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h21 \<- h19, -1 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Wait: h19 Read Inputs: h19 Write Outputs: h21 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h22 \<- h21, 0 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Read Inputs: h21 Write Outputs: h22 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h22, .L2 Wait: h22 Wait: h22 Wait: h22 Wait: h22 Wait: h22 Wait: h22 Wait: h22 Wait: h22 Read Inputs: h22 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h23 \<- h21, -1 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Wait: h21 Read Inputs: h21 Write Outputs: h23 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h24 \<- h23, 0 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Read Inputs: h23 Write Outputs: h24 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h24, .L2 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Wait: h24 Read Inputs: h24 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h25 \<- h23, -1 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Wait: h23 Read Inputs: h23 Write Outputs: h25 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h26 \<- h25, 0 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Read Inputs: h25 Write Outputs: h26 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h26, .L2 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Wait: h26 Read Inputs: h26 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h27 \<- h25, -1 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Wait: h25 Read Inputs: h25 Write Outputs: h27 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h28 \<- h27, 0 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Read Inputs: h27 Write Outputs: h28 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h28, .L2 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Wait: h28 Read Inputs: h28 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h29 \<- h27, -1 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Wait: h27 Read Inputs: h27 Write Outputs: h29 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h30 \<- h29, 0 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Read Inputs: h29 Write Outputs: h30 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h30, .L2 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Wait: h30 Read Inputs: h30 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: addi h31 \<- h29, -1 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Wait: h29 Read Inputs: h29 Write Outputs: h31 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: cmpdi h0 \<- h31, 0 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Read Inputs: h31 Write Outputs: h0 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Renamed: bne h0, .L2 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Wait: h0 Read Inputs: h0 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Renamed: addi h2 \<- h31, -1 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Wait: h31 Read Inputs: h31 Write Outputs: h2 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Renamed: cmpdi h1 \<- h2, 0 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Read Inputs: h2 Write Outputs: h1 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Renamed: bne h1, .L2 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Wait: h1 Read Inputs: h1 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Wait: not enough free regs Renamed: addi h4 \<- h2, -1 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Wait: h2 Read Inputs: h2 Write Outputs: h4 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Wait: not enough free regs Renamed: cmpdi h3 \<- h4, 0 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Read Inputs: h4 Write Outputs: h3 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Wait: not enough free regs Renamed: bne h3, .L2 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Wait: h3 Read Inputs: h3 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Wait: not enough free regs Wait: not enough free regs Renamed: addi h6 \<- h4, -1 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Wait: h4 Read Inputs: h4 Write Outputs: h6 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Wait: not enough free regs Wait: not enough free regs Renamed: cmpdi h5 \<- h6, 0 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Read Inputs: h6 Write Outputs: h5 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Wait: not enough free regs Renamed: bne h5, .L2 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Wait: h5 Read Inputs: h5 Write Outputs: Retire
0x100: addi r3 \<- r3, -1 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Wait: not enough free regs Wait: not enough free regs Renamed: addi h8 \<- h6, -1 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Wait: h6 Read Inputs: h6 Write Outputs: h8 Wait: Retire Retire
0x104: cmpdi r3, 0 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Wait: not enough free regs Wait: not enough free regs Renamed: cmpdi h7 \<- h8, 0 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Wait: h8 Read Inputs: h8 Write Outputs: h7 Retire
0x108: bne .L2 Fetch Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 Wait: not enough free regs Wait: not enough free regs Wait: not enough free regs Renamed: bne h7, .L2 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Wait: h7 Read Inputs: h7 Write Outputs: Retire