Draft Opcode tables

draft opcode tables

two major opcodes are needed

PO5 (temporary)

26-28 29.30 31 name Form
0 0 Rc ternlogi TLI-Form
0 0 0 0 1 crfternlogi CRB-Form
0 0 1 0 1 rsvd rsvd
0 1 / 0 1 / svshape4 SVI2-Form
1 0 n 0 1 rsvd rsvd
1 1 n 0 1 rsvd rsvd
1 iv 1 grevlogi TLI-Form
0 n n 1 0 0 madd/sub A-Form
1 1 0 crternlogi TLI-Form

madd/sub:

0.5 6.10 11.15 16.20 21..25 26....30 31 name Form
NN RT RA RB RC / 00 10 0 maddsubrs A-Form
NN RT RA RB RC / 01 10 0 maddrs A-Form
NN RT RA RB RC / 10 10 0 msubrs A-Form

PO22 - 2nd major opcode for other bitmanip: minor opcode allocation

28.30 31 name
-00 0 xpermi
-00 1 binary lut
-01 0 grevlog
-01 1 swizzle mv/fmv
010 Rc bitmask
011 SVP64
110 Rc 1/2-op
111 bmrevi

minmax is allocated to PO 19 XO 000011

1-op and variants

dest src1 subop op
RT RA .. bmatflip

2-op and variants

dest src1 src2 subop op
RT RA RB or bmatflip
RT RA RB xor bmatflip
RT RA RB grev
RT RA RB clmul*
RT RA RB gorc
RT RA RB shuf shuffle
RT RA RB unshuf shuffle
RT RA RB width xperm
RT RA RB MMM minmax
RT RA RB av abs avgadd
RT RA RB type vmask ops
RT RA RB type abs accumulate (overwrite)

3 ops

  • grevlog[w]
  • GF mul-add
  • bitmask-reverse

TODO: convert all instructions to use RT and not RS

0.5 6.10 11.15 16.20 21..25 26....30 31 name Form
NN RT RA it/im57 im0-4 0 00 00 0 xpermi TODO-Form
NN - 10 00 0 svshape3 rsvd
NN - 11 00 0 svshape4 rsvd
NN RT RA RB RC nh 00 00 1 binlut VA-Form
NN RT RA RB /BFA/ 0 01 00 1 bincrflut VA-Form
NN 1 01 00 1 svindex SVI-Form
NN RT RA RB mode L 10 00 1 bmask BM2-Form
NN 0 11 00 1 svshape SVM-Form
NN 1 11 00 1 svremap SVRM-Form
NN RT RA RB im0-4 im5-7 01 0 grevlog TLI-Form
NN - -- 01 1 swizzle mv/f TODO
NN RT RA RB RC mode 010 Rc bitmask* VA2-Form
NN FRS d1 d0 d0 00 011 d2 fmvis DX-Form
NN FRS d1 d0 d0 01 011 d2 fishmv DX-Form
NN 10 011 Rc svstep SVL-Form
NN 11 011 Rc setvl SVL-Form
NN ---- 110 1/2 ops other table [1]
NN RT RA RB RC 11 110 Rc bmrev VA2-Form
NN RT RA RB sh0-4 sh5 1 111 Rc bmrevi MDS-Form

[1] except bmrev

ops (note that av avg and abs as well as vec scalar mask are included here vector ops, and the av opcodes)

0.5 6.10 11.15 16.20 21 22.23 24....30 31 name Form
NN RS me sh SH ME 0 nn00 110 Rc bmopsi BM-Form
NN RS RA sh SH 0 1 nn00 110 Rc bmopsi XB-Form
NN RS RA im04 im5 1 1 im67 00 110 Rc bmatxori TODO
NN RT RA RB 1 00 0001 110 Rc cldiv X-Form
NN RT RA RB 1 01 0001 110 Rc clmod X-Form
NN RT RA 1 10 0001 110 Rc clmulh X-Form
NN RT RA RB 1 11 0001 110 Rc clmul X-Form
NN RT RA RB 0 00 0001 110 Rc rsvd
NN RT RA RB 0 01 0001 110 Rc rsvd
NN RT RA RB 0 10 0001 110 Rc rsvd
NN RT RA RB 0 11 0001 110 Rc vec cprop X-Form
NN 00 0101 110 0 crfbinlog CRB-Form
NN BT BA BFB// 0 00 0101 110 1 crbinlog X-Form
NN 1 00 0101 110 1 rsvd
NN 10 0101 110 Rc rsvd
NN RT RA RB sm0 sm1 1 0101 110 Rc shaddw X-Form
NN 0 1001 110 Rc rsvd
NN RT RA RB 1 00 1001 110 Rc av abss X-Form
NN RT RA RB 1 01 1001 110 Rc av absu X-Form
NN RT RA RB 1 10 1001 110 Rc av avgadd X-Form
NN RT RA RB 1 11 1001 110 Rc grevlutr X-Form
NN RT RA RB sm0 sm1 0 1101 110 Rc shadd X-Form
NN RT RA RB sm0 sm1 1 1101 110 Rc shadduw X-Form
NN RT RA RB 0 00 0010 110 Rc rsvd
NN RS RA sh SH 00 1010 110 Rc rsvd
NN RT RA RB 0 00 0110 110 Rc rsvd
NN RS RA SH 0 00 1110 110 Rc rsvd
NN RT RA RB 1 00 1110 110 Rc absds X-Form
NN RT RA RB 0 01 0010 110 Rc rsvd
NN RT RA RB 1 01 0010 110 Rc clmulr X-Form
NN RS RA sh SH 01 1010 110 Rc rsvd
NN RT RA RB 0 01 0110 110 Rc rsvd
NN RS RA SH 0 01 1110 110 Rc rsvd
NN RT RA RB 1 01 1110 110 Rc absdu X-Form
NN RS RA RB 0 10 0010 110 Rc bmator X-Form
NN RS RA RB 0 10 0110 110 Rc bmatand X-Form
NN RS RA RB 0 10 1010 110 Rc bmatxor X-Form
NN RS RA 0 10 1110 110 bmatflip X-Form
NN RT RA RB 1 10 0010 110 Rc xpermn X-Form
NN RT RA RB 1 10 0110 110 Rc xpermb X-Form
NN RT RA RB 1 10 1010 110 Rc xpermh X-Form
NN RT RA RB 1 10 1110 110 Rc xpermw X-Form
NN RT RA RB 0 11 1110 110 Rc absdacs X-Form
NN RT RA RB 1 11 1110 110 Rc absdacu X-Form
NN --11 110 Rc bmrev VA2-Form