fclass

based on xvtstdcsp v3.0B p760 the instruction performs analysis of the FP number to determine if it is Infinity, NaN, Denormalised or Zero and if so which sign. When VSX is not implemented these instructions become necessary.

unlike xvtstdcsp the result is stored in a Condition Register Field specified by BF. this allows it to be used as a predicate mask. setb may be used to create the equivalent of xvtstdcsp if desired.

The CR Field bits are set in a reasonably logical fashion:

• BF.EQ is set if FRB is zero
• BF.LE is set if FRB is non-normalises
• BF.GE is set if FRB is infinite
• BF.SO is set if FRB is NaN

dcmx <- DCMX || dm2
src  <- (FRB)[32:63]
sign  <- src[0]
exponent  <- src[1:8]
fraction  <- src[9:31]
class.Infinity  <- (exponent = 0xFF) & (fraction = 0)
class.NaN  <- (exponent = 0xFF) & (fraction != 0)
class.Zero  <- (exponent = 0x00) & (fraction = 0)
class.Denormal  <- (exponent = 0x00) & (fraction != 0)
CR{BF} <- ((dcmx[0] & class.NaN & !sign)  |
           (dcmx[1] & class.NaN & sign))  ||
          ((dcmx[2] & class.Infinity & !sign) |
           (dcmx[3] & class.Infinity & sign)) ||
          ((dcmx[6] & class.Denormal & !sign) |
           (dcmx[7] & class.Denormal & sign)) ||
          ((dcmx[4] & class.Zero & !sign) |
           (dcmx[5] & class.Zero & sign))

64 bit variant fptstdp is as follows:

src  <- (FRB)
sign <- src[0]
exponent <- src[1:11]
fraction <- src[12:63]
      exponent & 7FF

In SV just as with fcvt single precision is to be considered half-of-elwidth precision. Thus when elwidth=FP32 fptstsp will test half that precision, at FP16.