Example demonstration instruction modified to SVP64 (better)

Background: * https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56 * https://bugs.libre-soc.org/show_bug.cgi?id=1056#c63

The idea here is to review a modified version of a Power ISA 3 instruction definition, to add SVP64 in a completely non-disruptive fashion.

The proposal is therefore to add a clear alternative "Operand namespace", which already has precedent from EXT1xx-Prefixed instructions.

Assembler Syntax

a danger of even declaring the existence "sv.addi RT,RA,SI" is the assumption that it is different from addi RT,RA,SI. Alternative encodings that conflict with the Defined word-instruction (addi in this case) are flat-out prohibited in SVP64.

Vector/Scalar Operands

another danger - this one a permutation-explosion - exists when specifying which register operands are vector and which scalar: they all are, and they all are, independently of each other. this looks fine:

  • sv.addi RT,RA,SI
  • sv.addi RT,*RA,SI
  • sv.addi *RT,RA,SI
  • sv.addi *RT,*RA,SI

but this gets massively out of hand very quickly:

  • sv.fmadds FRT,FRA,FRB,FRC
  • ...
  • ...
  • sv.fmadds *FRT,*FRA,*FRB,*FRC

SVP64-annotated addi instruction (prototype)

Add Immediate D-Form

  • addi RT,RA,SI
    Defined Word-instruction: D-Form
        |    14 |   RT            |    RA       |     SI       |
        | 0     | 6               | 11          | 16        31 |
  • pseudocode.RA <- D-Form.RA
  • pseudocode.RT <- D-Form.RT
  • pseudocode.SI <- D-Form.SI

Prefixed Add Immediate MLS:D-form

  • paddi RT,RA,SI,R
    Prefix: MLS
        |    1  |   2    | 0 | // | R  | //  |     si0         |
        | 0     | 6      | 8 | 9  | 11 | 12  | 14           31 |

    Suffix:: D-Form
        |    14 |   RT            |    RA       | si1          |
        | 0     | 6               | 11          | 16        31 |

Operands:

  • pseudocode.RA <- D-Form.RA
  • pseudocode.RT <- D-Form.RT
  • pseudocode.SI <- MLS.si0 || MLS.si1

Vectorized Add Immediate SVP64-RM-1S1D/EXTRA3/Normal:D-form

  • sv.addi RT,RA,SI
    Prefix: SVP64-RM-1S1D/EXTRA3/Normal
        |    9  |  ..    |     Stuff | EXTRA    | MODEBITS     |
        | 0     | 6      | 8         | 17    26 | 27        31 |
    Defined Word-instruction: D-Form
        |    14 |   RT            |    RA       |     SI       |
        | 0     | 6               | 11          | 16        31 |

Operands:

  • pseudocode.RA <- SVP64_EXTRA3_DECODE(D-Form.RA, SVP64.RM.EXTRA[0:2])
  • pseudocode.RT <- SVP64_EXTRA3_DECODE(D-Form.RT, SVP64.RM.EXTRA[3:5])
  • pseudocode.SI <- D-Form.SI

Pseudo-code:

    if "addi" then
        RT <- (RA|0) + EXTS64(SI)
    if "paddi" & R=0 then
        RT <- (RA|0) + EXTS64(si0||si1)
    if "paddi" & R=1 then
        RT <- CIA + EXTS64(si0||si1)

Special Registers Altered:

    None