DRAFT Scalar Transcendentals

Summary:

This proposal extends Power ISA scalar floating point operations to add IEEE754 transcendental functions (pow, log etc) and trigonometric functions (sin, cos etc). These functions are also 98% shared with the Khronos Group OpenCL Extended Instruction Set.

Authors/Contributors:

• Luke Kenneth Casson Leighton
• Jacob Lifshay
• Dan Petroski
• Mitch Alsup
• Allen Baum
• Andrew Waterman
• Luis Vitorio Cargnini

See:

• http://bugs.libre-soc.org/show_bug.cgi?id=127
• https://bugs.libre-soc.org/show_bug.cgi?id=899 transcendentals in simulator
• https://bugs.libre-soc.org/show_bug.cgi?id=923 under review
• https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html
• power trans ops for opcode listing.

Extension subsets:

TODO: rename extension subsets -- we're not on RISC-V anymore.

• Zftrans: standard transcendentals (best suited to 3D)
• ZftransExt: extra functions (useful, not generally needed for 3D, can be synthesised using Ztrans)
• Ztrigpi: trig. xxx-pi sinpi cospi tanpi
• Ztrignpi: trig non-xxx-pi sin cos tan
• Zarctrigpi: arc-trig. a-xxx-pi: atan2pi asinpi acospi
• Zarctrignpi: arc-trig. non-a-xxx-pi: atan2, asin, acos
• Zfhyp: hyperbolic/inverse-hyperbolic. sinh, cosh, tanh, asinh, acosh, atanh (can be synthesised - see below)
• ZftransAdv: much more complex to implement in hardware
• Zfrsqrt: Reciprocal square-root.
• Zfminmax: Min/Max.

Minimum recommended requirements for 3D: Zftrans, Ztrignpi, Zarctrignpi, with Ztrigpi and Zarctrigpi as augmentations.

Minimum recommended requirements for Mobile-Embedded 3D: Ztrignpi, Zftrans, with Ztrigpi as an augmentation.

The Platform Requirements for 3D are driven by cost competitive factors and it is the Trademarked Vulkan Specification that provides clear direction for 3D GPU markets, but nothing else (IEEE754). Implementors must note that minimum Compliance with the Third Party Vulkan Specification (for power-area competitive reasons with other 3D GPU manufacturers) will not qualify for strict IEEE754 accuracy Compliance or vice-versa.

Implementors must make it clear which accuracy level is implemented and provide a switching mechanism and throw Illegal Instruction traps if fully compliant accuracy cannot be achieved. It is also the Implementor's responsibility to comply with all Third Party Certification Marks and Trademarks (Vulkan, OpenCL). Nothing in this specification in any way implies that any Third Party Certification Mark Compliance is granted, nullified, altered or overridden by this document.

TODO:

• Decision on accuracy, moved to zfpacc proposal http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002355.html
• Errors MUST be repeatable.
• How about four Platform Specifications? 3DUNIX, UNIX, 3DEmbedded and Embedded? http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002361.html Accuracy requirements for dual (triple) purpose implementations must meet the higher standard.
• Reciprocal Square-root is in its own separate extension (Zfrsqrt) as it is desirable on its own by other implementors. This to be evaluated.

Requirements

This proposal is designed to meet a wide range of extremely diverse needs, allowing implementors from all of them to benefit from the tools and hardware cost reductions associated with common standards adoption in Power ISA (primarily IEEE754 and Vulkan).

The use-cases are:

• 3D GPUs
• Numerical Computation
• (Potentially) A.I. / Machine-learning (1)

(1) although approximations suffice in this field, making it more likely to use a custom extension. High-end ML would inherently definitely be excluded.

The power and die-area requirements vary from:

• Ultra-low-power (smartwatches where GPU power budgets are in milliwatts)
• Mobile-Embedded (good performance with high efficiency for battery life)
• Desktop Computing
• Server / HPC / Supercomputing

The software requirements are:

• Full public integration into GNU math libraries (libm)
• Full public integration into well-known Numerical Computation systems (numpy)
• Full public integration into upstream GNU and LLVM Compiler toolchains
• Full public integration into Khronos OpenCL SPIR-V compatible Compilers seeking public Certification and Endorsement from the Khronos Group under their Trademarked Certification Programme.

Proposed Opcodes vs Khronos OpenCL vs IEEE754-2019

This list shows the (direct) equivalence between proposed opcodes, their Khronos OpenCL equivalents, and their IEEE754-2019 equivalents. 98% of the opcodes in this proposal that are in the IEEE754-2019 standard are present in the Khronos Extended Instruction Set.

See https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html and https://ieeexplore.ieee.org/document/8766229

• Special FP16 opcodes are not being proposed, except by indirect / inherent use of elwidth overrides that is already present in the SVP64 Specification.
• "Native" opcodes are not being proposed: implementors will be expected to use the (equivalent) proposed opcode covering the same function.
• "Fast" opcodes are not being proposed, because the Khronos Specification fast_length, fast_normalise and fast_distance OpenCL opcodes require vectors (or can be done as scalar operations using other Power ISA instructions).

The OpenCL FP32 opcodes are direct equivalents to the proposed opcodes. Deviation from conformance with the Khronos Specification - including the Khronos Specification accuracy requirements - is not an option, as it results in non-compliance, and the vendor may not use the Trademarked words "Vulkan" etc. in conjunction with their product.

IEEE754-2019 Table 9.1 lists "additional mathematical operations". Interestingly the only functions missing when compared to OpenCL are compound, exp2m1, exp10m1, log2p1, log10p1, pown (integer power) and powr.

from Mitch Alsup:

• Brian's LLVM compiler converts fminc and fmaxc into fmin and fmax instructions These are all IEEE 754-2019 compliant These are native instructions not extensions All listed functions are available in both F32 and F64 formats. THere is some confusion (in my head) abouot fmin and fmax. I intend both instruction to perform 754-2019 semantics-- but I don know if this is minimum/maximum or minimumNumber/maximumNumber. fmad and remainder are a 2-instruction sequence--don't know how to "edit it in"

Note (1) fsincos is macro-op fused (see below).

Note (2) synthesised in IEEE754-2019 as "rootn(x, 3)"

Note (3) synthesised in IEEE754-2019 using "1.0 / x"

Note (4) these are estimate opcodes that help accelerate software emulation

Note (5) f64-only (though can be used on f32 stored in f64 format), requires VSX.

Note (6) 4xf32-only, requires VMX.

List of 2-arg opcodes

Note (1): for the purposes of minNum/maxNum, -0.0 is defined to be less than +0.0. This is left unspecified in IEEE 754-2008.

Note (2): minmaxmag(x, y, cmp, fallback) is defined as:

def minmaxmag(x, y, is_max, fallback):
    a = abs(x) < abs(y)
    b = abs(x) > abs(y)
    if is_max:
        a, b = b, a  # swap
    if a:
        return x
    if b:
        return y
    # equal magnitudes, or NaN input(s)
    return fallback(x, y)

List of 1-arg transcendental opcodes

List of 1-arg trigonometric opcodes

Opcode Tables for PO=59/63 XO=1---011--

Power ISA v3.1B opcodes extracted from:

• Power ISA v3.1B Appendix D Table 23 sheet 2/3 of 4 page 1391/1392
• Power ISA v3.1B Appendix D Table 25 sheet 2/3 of 4 page 1399/1400

Parenthesized entries are not part of fptrans.

• Entries whose mnemonic ends in s are only in PO=59.
• Entries whose mnemonic does not end in s are only in PO=63.
• Entries whose mnemonic ends in (s) are in both PO=59 and PO=63.

DRAFT List of 2-arg opcodes

These are X-Form, recommended Major Opcode 63 for full-width and 59 for half-width (ending in s).

Recommended 10-bit XO assignments:

DRAFT List of 1-arg transcendental opcodes

These are X-Form, and are mostly identical in Special Registers Altered to fsqrt (the exact fp exceptions they can produce differ). Recommended Major Opcode 63 for full-width and 59 for half-width (ending in s).

Special Registers Altered (FIXME: come up with correct list):

FPRF FR FI FX OX UX XX
VXSNAN VXIMZ VXZDZ
CR1                    (if Rc=1)

Recommended 10-bit XO assignments:

DRAFT List of 1-arg trigonometric opcodes

These are X-Form, and are mostly identical in Special Registers Altered to fsqrt (the exact fp exceptions they can produce differ). Recommended Major Opcode 63 for full-width and 59 for half-width (ending in s)

Special Registers Altered:

FPRF FR FI FX OX UX XX
VXSNAN VXIMZ VXZDZ
CR1                    (if Rc=1)

Recommended 10-bit XO assignments:

Subsets

The full set is based on the Khronos OpenCL opcodes. If implemented entirely it would be too much for both Embedded and also 3D.

The subsets are organised by hardware complexity, need (3D, HPC), however due to synthesis producing inaccurate results at the range limits, the less common subsets are still required for IEEE754 HPC.

MALI Midgard, an embedded / mobile 3D GPU, for example only has the following opcodes:

28 - fmin
2C - fmax
E8 - fatan_pt2
F0 - frcp (reciprocal)
F2 - frsqrt (inverse square root, 1/sqrt(x))
F3 - fsqrt (square root)
F4 - fexp2 (2^x)
F5 - flog2
F6 - fsin1pi
F7 - fcos1pi
F9 - fatan_pt1

These in FP32 and FP16 only: no FP64 hardware, at all.

Vivante Embedded/Mobile 3D (etnaviv https://github.com/laanwj/etna_viv/blob/master/rnndb/isa.xml) only has the following:

fmin/fmax (implemented using SELECT)
sin, cos2pi
cos, sin2pi
log2, exp
sqrt and rsqrt
recip.

It also has fast variants of some of these, as a CSR Mode.

AMD's R600 GPU (R600_Instruction_Set_Architecture.pdf) and the RDNA ISA (RDNA_Shader_ISA_5August2019.pdf, Table 22, Section 6.3) have:

MIN/MAX/MIN_DX10/MAX_DX10
COS2PI (appx)
EXP2
LOG (IEEE754)
RECIP
RSQRT
SQRT
SIN2PI (appx)

AMD RDNA has F16 and F32 variants of all the above, and also has F64 variants of SQRT, RSQRT, MIN, MAX, and RECIP. It is interesting that even the modern high-end AMD GPU does not have TAN or ATAN, where MALI Midgard does.

Also a general point, that customised optimised hardware targetting FP32 3D with less accuracy simply can neither be used for IEEE754 nor for FP64 (except as a starting point for hardware or software driven Newton Raphson or other iterative method).

Also in cost/area sensitive applications even the extra ROM lookup tables for certain algorithms may be too costly.

These wildly differing and incompatible driving factors lead to the subset subdivisions, below.

Transcendental Subsets

Zftrans

LOG2 EXP2 RECIP RSQRT

Zftrans contains the minimum standard transcendentals best suited to 3D. They are also the minimum subset for synthesising log10, exp10, exp1m, log1p, the hyperbolic trigonometric functions sinh and so on.

They are therefore considered "base" (essential) transcendentals.

ZftransExt

LOG, EXP, EXP10, LOG10, LOGP1, EXP1M, fmod, fremainder

These are extra transcendental functions that are useful, not generally needed for 3D, however for Numerical Computation they may be useful.

Although they can be synthesised using Ztrans (LOG2 multiplied by a constant), there is both a performance penalty as well as an accuracy penalty towards the limits, which for IEEE754 compliance is unacceptable. In particular, LOG(1+FRA) in hardware may give much better accuracy at the lower end (very small FRA) than LOG(FRA).

Their forced inclusion would be inappropriate as it would penalise embedded systems with tight power and area budgets. However if they were completely excluded the HPC applications would be penalised on performance and accuracy.

Therefore they are their own subset extension.

Zfhyp

SINH, COSH, TANH, ASINH, ACOSH, ATANH

These are the hyperbolic/inverse-hyperbolic functions. Their use in 3D is limited.

They can all be synthesised using LOG, SQRT and so on, so depend on Zftrans. However, once again, at the limits of the range, IEEE754 compliance becomes impossible, and thus a hardware implementation may be required.

HPC and high-end GPUs are likely markets for these.

ZftransAdv

CBRT, POW, POWN, POWR, ROOTN

These are simply much more complex to implement in hardware, and typically will only be put into HPC applications.

Note that pow is commonly used in Blinn-Phong shading (the shading model used by OpenGL 1.0 and commonly used by shader authors that need basic 3D graphics with specular highlights), however it can be sufficiently emulated using pow(b, n) = exp2(n*log2(b)).

• Zfrsqrt: Reciprocal square-root.

Trigonometric subsets

Ztrigpi vs Ztrignpi

• Ztrigpi: SINPI COSPI TANPI
• Ztrignpi: SIN COS TAN

Ztrignpi are the basic trigonometric functions through which all others could be synthesised, and they are typically the base trigonometrics provided by GPUs for 3D, warranting their own subset.

(programmerjake: actually, all other GPU ISAs mentioned in this document have sinpi/cospi or equivalent, and often not sin/cos, because sinpi/cospi are actually waay easier to implement because range reduction is simply a bitwise mask, whereas for sin/cos range reduction is a full division by pi)

(Mitch: My patent USPTO 10,761,806 shows that the above statement is no longer true.)

In the case of the Ztrigpi subset, these are commonly used in for loops with a power of two number of subdivisions, and the cost of multiplying by PI inside each loop (or cumulative addition, resulting in cumulative errors) is not acceptable.

In for example CORDIC the multiplication by PI may be moved outside of the hardware algorithm as a loop invariant, with no power or area penalty.

Again, therefore, if SINPI (etc.) were excluded, programmers would be penalised by being forced to divide by PI in some circumstances. Likewise if SIN were excluded, programmers would be penaslised by being forced to multiply by PI in some circumstances.

Thus again, a slightly different application of the same general argument applies to give Ztrignpi and Ztrigpi as subsets. 3D GPUs will almost certainly provide both.

Zarctrigpi and Zarctrignpi

• Zarctrigpi: ATAN2PI ASINPI ACOSPI
• Zarctrignpi: ATAN2 ACOS ASIN

These are extra trigonometric functions that are useful in some applications, but even for 3D GPUs, particularly embedded and mobile class GPUs, they are not so common and so are typically synthesised, there.

Although they can be synthesised using Ztrigpi and Ztrignpi, there is, once again, both a performance penalty as well as an accuracy penalty towards the limits, which for IEEE754 compliance is unacceptable, yet is acceptable for 3D.

Therefore they are their own subset extensions.

Zfminmax

• fminnum08 fmaxnum08
• fmin19 fmax19
• fminnum19 fmaxnum19
• fminc fmaxc
• fminmagnum08 fmaxmagnum08
• fminmag19 fmaxmag19
• fminmagnum19 fmaxmagnum19
• fminmagc fmaxmagc

These are commonly used for vector reductions, where having them be a single instruction is critical. They are also commonly used in GPU shaders, HPC, and general-purpose FP algorithms.

These min and max operations are quite cheap to implement hardware-wise, being comparable in cost to fcmp + some muxes. They're all in one extension because once you implement some of them, the rest require only slightly more hardware complexity.

Therefore they are their own subset extension.

Synthesis, Pseudo-code ops and macro-ops

The pseudo-ops are best left up to the compiler rather than being actual pseudo-ops, by allocating one scalar FP register for use as a constant (loop invariant) set to "1.0" at the beginning of a function or other suitable code block.

• fsincos - fused macro-op between fsin and fcos (issued in that order).
• fsincospi - fused macro-op between fsinpi and fcospi (issued in that order).

fatanpi example pseudo-code:

fmvis ft0, 0x3F80 // upper bits of f32 1.0 (BF16)
fatan2pis FRT, FRA, ft0

Hyperbolic function example (obviates need for Zfhyp except for high-performance or correctly-rounding):

ASINH( x ) = ln( x + SQRT(x**2+1))

pow sufficient for 3D Graphics:

pow(b, x) = exp2(x * log2(b))

Evaluation and commentary

Moved to discussion