AXI Bridge

See also wishbone Bus

• http://bugs.libre-riscv.org/show_bug.cgi?id=10
• https://github.com/alexforencich/verilog-axis
• https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl

AXI4 in migen

Implementations of AXI4 in nmigen (not just bridges)

• https://github.com/peteut/migen-axi
• https://github.com/apertus-open-source-cinema/nmigen-gateware
• nmigen-soc planning to have AXI4