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DDR (DRAM) Controller and PHY

  • https://github.com/enjoy-digital/litedram - controller inc. DDR3 / LPDDR3
  • https://www.ohwr.org/projects/ddr3-sp6-core/wiki/wiki - CERN DDR3 ctrl
  • https://www.linkedin.com/in/michael-taylor-32212816/ working on DDR3 IO Cells
  • https://github.com/waviousllc/wav-lpddr-hw
  • https://github.com/ZiyangYE/General-Slow-DDR3-Interface
  • https://github.com/ultraembedded/core_ddr3_controller
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Links: m class Last edited Thu Aug 18 10:00:20 2022.