Cole Poirier (cole)

Status Tracking

Currently working on

• Bug #340: formal proof of POWER9 SHIFTROT pipeline needed
• Bug #448: MUL pipeline unit tests
• Bug #450: Create MMU from microwatt mmu.vhdl

Paid by NLNet

NLNet.2019.10.Wishbone

• Bug #325: create POWER9 TRAP pipeline
  • submitted on 2020-09-20
  • paid on 2020-10-01
  • €100 out of total of €500
• Bug #351: create a "block" (mass) regfile port (read and write) onto an array-based regfile
  • submitted on 2020-09-20
  • paid on 2020-10-01
  • €100 out of total of €200
• Bug #401: Convert Memory Architecture diagram from hand-drawn to editable SVG
  • submitted on 2020-09-20
  • paid on 2020-10-01
  • €150 which is the total amount
• Bug #404: adding nmigen-soc as a dependency needs documentation updated
  • submitted on 2020-09-20
  • paid on 2020-10-01
  • €100 which is the total amount
• Bug #472: tutorial and dev page needed for mesa driver
  • submitted on 2020-09-20
  • paid on 2020-10-01
  • €100 which is the total amount
• Bug #493: DMI JTAG TAP needed
  • paid on 2021-05-05
  • €150 out of total of €400

NLNet.2019.Coriolis2

• Bug #178: first coriolis2 tutorial, workflow and "test project" page
  • paid on 2020-12-20
  • €500 out of total of €3000
• Bug #291: HDL Workflow and Coriolis2 chroot automated setup scripts
  • submitted on 2020-09-20
  • paid on 2020-10-01
  • €200 which is the total amount
• Bug #502: determine SRAM block size and implement it
  • paid on 2021-05-05
  • €50 out of total of €1250