Luke Kenneth Casson Leighton

Status Tracking

Currently working on

  • Bug #24: pinmux memory map
  • Bug #26: pinmux default mux values
  • Bug #34: pinmux add sdram interface
  • Bug #36: pinmux split out #defines from bsv to includes
  • Bug #57: chain of buffered pipeline followed by unbuffered pipeline fails
  • Bug #335: Formal Correctness Proof for Branch pipeline
  • Bug #432: mulld pseudocode overflow calculation incorrect
  • Bug #609: set SVSTATE over DMI and JTAG interface

Completed but not yet added to payees list

  • Bug #101: IEEE754 pipeline "go_die" (Computation Unit Cancellation) needed
  • Bug #172: partitioned signal add/sub/neg
  • Bug #466: comprehensive evaluation and planning for 3D MESA driver

Submitted to NLNet but not yet paid

NLNet.2019.10.Formal

  • Bug #335: Formal Correctness Proof for Branch pipeline
    • submitted on 2020-12-06
    • €300 out of total of €400
  • Bug #335: Formal Correctness Proof for Branch pipeline
    • submitted on 2020-12-06
    • €100 out of total of €400
  • Bug #418: SPR pipeline formal correctness proof needed
    • submitted on 2021-04-24
    • €50 out of total of €400
  • Bug #419: MUL pipeline formal proof needed
    • submitted on 2021-04-24
    • €50 out of total of €550

NLNet.2019.10.Wishbone

  • Bug #305: Create Pipelined ALU similar to alu_hier.py
    • submitted on 2021-04-24
    • €200 out of total of €400
  • Bug #313: Create Branch Pipeline for POWER9
    • submitted on 2021-04-24
    • €150 out of total of €250
  • Bug #314: Create POWER9 Condition Register pipeline
    • submitted on 2021-04-24
    • €200 out of total of €300
  • Bug #330: create POWER9 Logic Pipeline
    • submitted on 2021-04-24
    • €150 out of total of €300
  • Bug #348: POWER9 SPR pipeline needed
    • submitted on 2020-12-06
    • €250 out of total of €300
  • Bug #349: privileged-instruction decoding function needed
    • submitted on 2020-12-06
    • €100 which is the total amount
  • Bug #407: XICS interrupt controller is needed
    • submitted on 2020-12-06
    • €450 which is the total amount
  • Bug #416: dec and tb POWER9 SPRs needed
    • submitted on 2020-12-06
    • €200 which is the total amount
  • Bug #426: LDST sign-extension support needed
    • submitted on 2020-12-06
    • €100 which is the total amount
  • Bug #427: LDST cache-inhibit instructions needed (l*cix, st*cix)
    • submitted on 2021-04-24
    • €200 which is the total amount
  • Bug #468: wishbone downconverter needed
    • submitted on 2020-12-06
    • €200 which is the total amount
  • Bug #476: addme ALU pipeline bug
    • submitted on 2020-12-06
    • €100 which is the total amount
  • Bug #478: MFOCR and MCROF need to be one-hot
    • submitted on 2020-12-06
    • €200 which is the total amount
  • Bug #493: DMI JTAG TAP needed
    • submitted on 2020-12-06
    • €250 out of total of €400
  • Bug #556: document SV OpenPOWER
    • submitted on 2021-04-24
    • €900 out of total of €1000

NLNet.2019.Coriolis2

  • Bug #202: potential changes to LibreSOC HDL to suit coriolis2
    • submitted on 2021-04-24
    • €3000 out of total of €6000
  • Bug #490: Complete peripheral set including litex for first functional OpenPOWER Core (ls180)
    • submitted on 2021-04-24
    • €1750 out of total of €2000
  • Bug #502: determine SRAM block size and implement it
    • submitted on 2021-04-24
    • €300 out of total of €1250
  • Bug #506: 8x VDD VSS pins needed in ioring
    • submitted on 2021-04-24
    • €450 out of total of €600
  • Bug #507: ls180 asic needs an ioring, pads need defining and connecting
    • submitted on 2020-12-06
    • €750 out of total of €1500
  • Bug #508: decide package size and pin allocation for 180nm ASIC
    • submitted on 2020-12-06
    • €50 out of total of €100
  • Bug #521: small example using JTAG for testing coriolis2 new multi clock plugin
    • submitted on 2020-12-06
    • €300 out of total of €400
  • Bug #620: post-layout simulation needed using cocotb
    • submitted on 2021-04-24
    • €1250 out of total of €2500

NLNet.2019.Video

  • Bug #557: First round of development of Audio/Video opcodes
    • submitted on 2021-04-24
    • €1100 out of total of €2000

Paid by NLNet

NLnet.2019.02

  • Bug #43: create an IEEE754 FP "sqrt"
    • paid on 2019-08-10
    • €480 out of total of €1200
  • Bug #44: IEEE754 FPU inverse (reciprocal) sqrt
    • paid on 2019-08-10
    • €600 out of total of €1500
  • Bug #63: queue (FIFO) library routine needed
    • paid on 2019-11-19
    • €400 out of total of €800
  • Bug #68: nmigen general utils needed
    • paid on 2019-11-19
    • €500 which is the total amount
  • Bug #71: option to replace SetAssocCache PLRU with random selection (LFSR)
    • paid on 2019-06-04
    • €250 out of total of €500
  • Bug #73: all nmigen module-based classes now need to derive from Elaboratable
    • paid on 2019-06-16
    • €500 which is the total amount
  • Bug #75: create an IEEE754 FP "add" pipeline
    • paid on 2019-06-04
    • €1500 which is the total amount
  • Bug #77: IEEE754 FP "mul" needed
    • paid on 2019-07-10
    • €2000 which is the total amount
  • Bug #78: IEEE754 FP "div" needed
    • paid on 2019-06-16
    • €1000 which is the total amount
  • Bug #86: 6600-style preliminary investigation
    • paid on 2019-06-04
    • €1000 which is the total amount
  • Bug #94: implement load/store memory dependency matrix
    • submitted on 2020-12-06
    • paid on 2020-12-20
    • €1500 which is the total amount
  • Bug #95: implement shadowing for use in precise exceptions, branch speculation, predication and WaW ordering
    • paid on 2019-06-16
    • €1000 which is the total amount
  • Bug #99: IEEE754 *pipelined* FPDIV unit needed
    • paid on 2019-08-10
    • €400 out of total of €1000
  • Bug #107: IEEE754 FPU FCVT "downconversion" needed
    • paid on 2019-07-10
    • €750 which is the total amount
  • Bug #108: IEEE754 FPU FCVT "upconversion" needed
    • paid on 2019-07-30
    • €250 which is the total amount
  • Bug #111: FCVT unsigned/signed char/short/int/long (8/16/32/64) to FP16/32/64 needed
    • paid on 2019-07-30
    • €125 which is the total amount
  • Bug #112: FCVT FP16/32/64 to unsigned/signed char/short/int/long (8/16/32/64) needed
    • paid on 2019-07-30
    • €125 which is the total amount
  • Bug #113: FCVT unit tests have too great a dynamic range
    • paid on 2020-03-12
    • €250 which is the total amount
  • Bug #117: RISCV FCLASS instruction needed
    • paid on 2019-07-30
    • €125 which is the total amount
  • Bug #127: Transcendentals needed (SIN/COS/ATAN2/EXP/LOG/POW etc.)
    • paid on 2020-03-12
    • €900 out of total of €1250
  • Bug #148: single chain pipeline API needed
    • paid on 2019-11-19
    • €750 out of total of €1500
  • Bug #171: partitioned comparison operators
    • paid on 2020-03-12
    • €200 out of total of €400
  • Bug #173: dynamic partitioned "shift"
    • paid on 2020-03-12
    • €350 out of total of €700
  • Bug #208: implement CORDIC in a general way sufficient to do transcendentals
    • submitted on 2020-12-06
    • paid on 2020-12-20
    • €750 which is the total amount
  • Bug #292: implement multi-way read/write 6600 signals
    • paid on 2020-04-28
    • €600 which is the total amount
  • Bug #412: set up litex for peripherals and linking to core
    • paid on 2020-09-04
    • €1200 out of total of €2000
  • Bug #538: development of Stage API and pipeline API
    • submitted on 2020-12-06
    • paid on 2020-12-20
    • €700 out of total of €1200

NLNet.2019.10.Formal

  • Bug #306: Formal Correctness Proof for ALU pipeline
    • paid on 2020-12-06
    • €400 out of total of €500
  • Bug #312: Formal Correctness Proof for CountZero needed (basically PriorityEncoder)
    • paid on 2020-08-21
    • €150 which is the total amount
  • Bug #331: Formal Correctness Proof for LOGICAL pipeline
    • submitted on 2020-12-06
    • paid on 2020-12-09
    • €300 out of total of €400
  • Bug #331: Formal Correctness Proof for LOGICAL pipeline
    • submitted on 2020-08-21
    • paid on 2020-08-21
    • €100 out of total of €400
  • Bug #332: Formal correctness proof needed for CR pipeline
    • paid on 2020-12-06
    • €300 which is the total amount
  • Bug #421: TRAP pipeline formal correctness proof needed
    • paid on 2020-10-19
    • €100 out of total of €500

NLNet.2019.10.Standards

  • Bug #269: auto-conversion / parser of POWER ISA Spec v3.0B
    • paid on 2020-04-27
    • €500 out of total of €1000
  • Bug #272: functions needed in POWER simulator which match 3.0B spec
    • paid on 2020-10-19
    • €50 out of total of €250
  • Bug #463: python based cycle accurate POWER9 simulator
    • paid on 2020-08-10
    • €1000 out of total of €2000

NLNet.2019.10.Wishbone

  • Bug #186: Create decoder for SOC: Power ISA
    • paid on 2020-10-21
    • €200 out of total of €500
  • Bug #186: Create decoder for SOC: Power ISA
    • paid on 2020-12-06
    • €200 out of total of €500
  • Bug #305: Create Pipelined ALU similar to alu_hier.py
    • paid on 2020-08-21
    • €200 out of total of €400
  • Bug #313: Create Branch Pipeline for POWER9
    • paid on 2020-08-21
    • €100 out of total of €250
  • Bug #314: Create POWER9 Condition Register pipeline
    • paid on 2020-08-21
    • €100 out of total of €300
  • Bug #323: create POWER9 MUL pipeline
    • paid on 2020-08-21
    • €250 out of total of €750
  • Bug #324: create POWER DIV pipeline
    • paid on 2020-08-14
    • €500 out of total of €1500
  • Bug #325: create POWER9 TRAP pipeline
    • paid on 2020-10-01
    • €300 out of total of €500
  • Bug #330: create POWER9 Logic Pipeline
    • paid on 2020-08-21
    • €150 out of total of €300
  • Bug #339: create POWER9 ROTATE (SHIFTROT) pipeline
    • paid on 2020-08-21
    • €300 which is the total amount
  • Bug #344: missing mtmsr and mfsprd
    • paid on 2020-08-21
    • €100 which is the total amount
  • Bug #345: define POWER9 regfiles
    • paid on 2020-08-21
    • €200 which is the total amount
  • Bug #346: simplified test link between compunits and regfile
    • paid on 2020-08-21
    • €750 which is the total amount
  • Bug #351: create a "block" (mass) regfile port (read and write) onto an array-based regfile
    • paid on 2020-10-01
    • €100 out of total of €200
  • Bug #382: nmigen wishbone Memory (SRAM) object needed
    • paid on 2020-08-21
    • €150 which is the total amount
  • Bug #393: Hook up augmented-Wishbone Memory Bus to LDSTCompUnit (via PortInterface)
    • paid on 2020-08-21
    • €300 which is the total amount
  • Bug #409: deal with illegal instruction in simulator and hardware
    • paid on 2020-08-21
    • €100 which is the total amount
  • Bug #414: debug port needed (JTAG, other frontend)
    • paid on 2020-08-21
    • €250 which is the total amount
  • Bug #435: PC and MSR need to be in the "state" (Decode2Execute1Type)
    • paid on 2020-08-19
    • €100 which is the total amount
  • Bug #441: Avoid unit tests that depend on other unit tests being run first
    • paid on 2020-08-21
    • €200 out of total of €400
  • Bug #460: Documenting the Out of Order architecture
    • paid on 2020-08-21
    • €500 which is the total amount

NLNet.2019.Coriolis2

  • Bug #178: first coriolis2 tutorial, workflow and "test project" page
    • paid on 2020-03-14
    • €1200 out of total of €3000

NLNet.2019.Video

  • Bug #147: sv2nmigen now converts module headers
    • paid on 2020-01-28
    • €250 out of total of €1000