Michael Nolan

Status Tracking

Completed but not yet added to payees list

  • Bug #120: implement RISC-V FSGNJ instruction
  • Bug #129: FP comparisons needed
  • Bug #130: FMIN/MAX needed
  • Bug #162: Formally Verify the FSGNJ module
  • Bug #163: Formally Verify the FPMAX module
  • Bug #165: Formally verify the FPCMP (FEQ, FLE, FLT) module
  • Bug #189: Create partitioned right shift using the existing partitioned left shift
  • Bug #305: Create Pipelined ALU similar to alu_hier.py
  • Bug #313: Create Branch Pipeline for POWER9
  • Bug #314: Create POWER9 Condition Register pipeline
  • Bug #330: create POWER9 Logic Pipeline
  • Bug #332: Formal correctness proof needed for CR pipeline
  • Bug #339: create POWER9 ROTATE (SHIFTROT) pipeline

Completed but not yet paid

NLnet.2019.02

  • Bug #171: partitioned comparison operators
    • €200 out of total of €400
  • Bug #173: dynamic partitioned "shift"
    • €350 out of total of €700

NLNet.2019.10.Standards

  • Bug #463: python based cycle accurate POWER9 simulator
    • €1000 out of total of €2000

Paid by NLNet

NLNet.2019.10.Standards

  • Bug #269: auto-conversion / parser of POWER ISA Spec v3.0B
    • paid on 2020-04-27
    • €500 out of total of €1000
  • Bug #272: functions needed in POWER simulator which match 3.0B spec
    • paid on 2020-10-19
    • €200 out of total of €250