Staf Verhaegen

Status Tracking

Completed but not yet paid

NLNet.2019.Coriolis2

  • Bug #178: first coriolis2 tutorial, workflow and "test project" page
    • €150 out of total of €3000
  • Bug #204: Transition from symbolic to real Cell Library for 180nm layout
    • €5000 which is the total amount
  • Bug #508: decide package size and pin allocation for 180nm ASIC
    • €50 out of total of €100

Submitted to NLNet but not yet paid

NLNet.2019.Coriolis2

  • Bug #202: potential changes to LibreSOC HDL to suit coriolis2
    • submitted on 2021-04-21
    • €3000 out of total of €6000
  • Bug #490: Complete peripheral set including litex for first functional OpenPOWER Core (ls180)
    • submitted on 2021-04-24
    • €250 out of total of €2000
  • Bug #502: determine SRAM block size and implement it
    • submitted on 2021-04-21
    • €900 out of total of €1250
  • Bug #506: 8x VDD VSS pins needed in ioring
    • submitted on 2021-04-21
    • €150 out of total of €600
  • Bug #620: post-layout simulation needed using cocotb
    • submitted on 2021-04-21
    • €1250 out of total of €2500