Ternary Bitwise Logic Immediate
TLI-Form
- ternlogi RT,RA,RB,TLI (Rc=0)
- ternlogi. RT,RA,RB,TLI (Rc=1)
Pseudo-code:
result <- [0] * XLEN
do i = 0 to XLEN - 1
idx <- (RT)[i] || (RA)[i] || (RB)[i]
result[i] <- TLI[7-idx]
RT <- result
Special Registers Altered:
CR0 (if Rc=1)
Add With Shift By Immediate
Z23-Form
- sadd RT,RA,RB,SH (Rc=0)
- sadd. RT,RA,RB,SH (Rc=1)
Pseudo-code:
n <- (RB)
m <- ((0b0 || SH) + 1)
RT <- (n[m:XLEN-1] || [0]*m) + (RA)
Special Registers Altered:
CR0 (if Rc=1)
Add With Shift By Immediate Word
Z23-Form
- saddw RT,RA,RB,SH (Rc=0)
- saddw. RT,RA,RB,SH (Rc=1)
Pseudo-code:
n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
if (RB)[XLEN/2] = 1 then
n[0:XLEN/2-1] <- [1]*(XLEN/2)
m <- ((0b0 || SH) + 1)
RT <- (n[m:XLEN-1] || [0]*m) + (RA)
Special Registers Altered:
CR0 (if Rc=1)
Add With Shift By Immediate Unsigned Word
Z23-Form
- sadduw RT,RA,RB,SH (Rc=0)
- sadduw. RT,RA,RB,SH (Rc=1)
Pseudo-code:
n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
m <- ((0b0 || SH) + 1)
RT <- (n[m:XLEN-1] || [0]*m) + (RA)
Special Registers Altered:
CR0 (if Rc=1)