ISA Reference Tables
These are from 3.0B p1145 Appendix C, and are based on Anton Blanchard's microwatt decode1.vhdl
Major opcodes
decodes using f_in.insn(31 downto 26)
opcode | unit | internal op | in1 | in2 | in3 | out | CR in | CR out | inv A | inv out | cry in | cry out | ldst len | BR | sgn ext | upd | rsrv | 32b | sgn | rc | lk | sgl pipe | comment | form |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
12 | ALU | OP_ADD | RA | CONST_SI | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | addic | D |
13 | ALU | OP_ADD | RA | CONST_SI | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | ONE | 0 | 0 | addic. | D |
14 | ALU | OP_ADD | RA_OR_ZERO | CONST_SI | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | addi | D |
15 | ALU | OP_ADD | RA_OR_ZERO | CONST_SI_HI | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | addis | D |
17 | TRAP | OP_SC | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | sc | SC |
28 | LOGICAL | OP_AND | RS | CONST_UI | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | ONE | 0 | 0 | andi. | B |
29 | LOGICAL | OP_AND | RS | CONST_UI_HI | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | ONE | 0 | 0 | andis. | B |
18 | BRANCH | OP_B | NONE | CONST_LI | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 1 | 0 | b | I |
16 | BRANCH | OP_BC | SPR | CONST_BD | NONE | SPR | BI | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 1 | 0 | bc | B |
11 | ALU | OP_CMP | RA | CONST_SI | NONE | NONE | NONE | BF | 1 | 0 | ONE | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | NONE | 0 | 0 | cmpi | D |
10 | ALU | OP_CMP | RA | CONST_UI | NONE | NONE | NONE | BF | 1 | 0 | ONE | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | cmpli | D |
34 | LDST | OP_LOAD | RA_OR_ZERO | CONST_SI | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lbz | D |
35 | LDST | OP_LOAD | RA_OR_ZERO | CONST_SI | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | lbzu | D |
42 | LDST | OP_LOAD | RA_OR_ZERO | CONST_SI | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 1 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lha | D |
43 | LDST | OP_LOAD | RA_OR_ZERO | CONST_SI | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 1 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | lhau | D |
40 | LDST | OP_LOAD | RA_OR_ZERO | CONST_SI | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lhz | D |
41 | LDST | OP_LOAD | RA_OR_ZERO | CONST_SI | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | lhzu | D |
32 | LDST | OP_LOAD | RA_OR_ZERO | CONST_SI | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lwz | D |
33 | LDST | OP_LOAD | RA_OR_ZERO | CONST_SI | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | lwzu | D |
7 | MUL | OP_MUL_L64 | RA | CONST_SI | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | NONE | 0 | 0 | mulli | D |
24 | LOGICAL | OP_OR | RS | CONST_UI | NONE | RA | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | ori | D |
25 | LOGICAL | OP_OR | RS | CONST_UI_HI | NONE | RA | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | oris | D |
20 | SHIFT_ROT | OP_RLC | RA | CONST_SH32 | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | rlwimi | M |
21 | SHIFT_ROT | OP_RLC | NONE | CONST_SH32 | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | rlwinm | M |
23 | SHIFT_ROT | OP_RLC | NONE | RB | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | rlwnm | M |
38 | LDST | OP_STORE | RA_OR_ZERO | CONST_SI | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | stb | D |
39 | LDST | OP_STORE | RA_OR_ZERO | CONST_SI | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | stbu | D |
44 | LDST | OP_STORE | RA_OR_ZERO | CONST_SI | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | sth | D |
45 | LDST | OP_STORE | RA_OR_ZERO | CONST_SI | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | sthu | D |
36 | LDST | OP_STORE | RA_OR_ZERO | CONST_SI | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | stw | D |
37 | LDST | OP_STORE | RA_OR_ZERO | CONST_SI | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | stwu | D |
8 | ALU | OP_ADD | RA | CONST_SI | NONE | RT | NONE | NONE | 1 | 0 | ONE | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | subfic | D |
2 | TRAP | OP_TRAP | RA | CONST_SI | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | tdi | D |
3 | TRAP | OP_TRAP | RA | CONST_SI | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | NONE | 0 | 1 | twi | D |
26 | LOGICAL | OP_XOR | RS | CONST_UI | NONE | RA | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | xori | D |
27 | LOGICAL | OP_XOR | RS | CONST_UI_HI | NONE | RA | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | xoris | D |
Minor opcode 19
decodes using f_in.insn(5 downto 1)
opcode | unit | internal op | in1 | in2 | in3 | out | CR in | CR out | inv A | inv out | cry in | cry out | ldst len | BR | sgn ext | upd | rsrv | 32b | sgn | rc | lk | sgl pipe | comment | form |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0b00010 | ALU | OP_ILLEGAL | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 1 | add pcis not implemented yet | DX |
decodes using f_in.insn(10 downto 1)
opcode | unit | internal op | in1 | in2 | in3 | out | CR in | CR out | inv A | inv out | cry in | cry out | ldst len | BR | sgn ext | upd | rsrv | 32b | sgn | rc | lk | sgl pipe | comment | form |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0b0000000000 | CR | OP_MCRF | NONE | NONE | NONE | NONE | BFA | BF | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | mcrf | XL |
0b0100000001 | CR | OP_CROP | NONE | NONE | NONE | NONE | BA_BB | BT | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | crand | XL |
0b0010000001 | CR | OP_CROP | NONE | NONE | NONE | NONE | BA_BB | BT | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | crandc | XL |
0b0100100001 | CR | OP_CROP | NONE | NONE | NONE | NONE | BA_BB | BT | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | creqv | XL |
0b0011100001 | CR | OP_CROP | NONE | NONE | NONE | NONE | BA_BB | BT | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | crnand | XL |
0b0000100001 | CR | OP_CROP | NONE | NONE | NONE | NONE | BA_BB | BT | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | crnor | XL |
0b0111000001 | CR | OP_CROP | NONE | NONE | NONE | NONE | BA_BB | BT | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | cror | XL |
0b0110100001 | CR | OP_CROP | NONE | NONE | NONE | NONE | BA_BB | BT | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | crorc | XL |
0b0011000001 | CR | OP_CROP | NONE | NONE | NONE | NONE | BA_BB | BT | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | crxor | XL |
0b1000010000 | BRANCH | OP_BCREG | SPR | SPR | NONE | SPR | BI | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 1 | 0 | bcctr | XL |
0b0000010000 | BRANCH | OP_BCREG | SPR | SPR | NONE | SPR | BI | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 1 | 0 | bclr | XL |
0b1000110000 | BRANCH | OP_BCREG | SPR | SPR | NONE | SPR | BI | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 1 | 0 | bctar | XL |
0b0010010110 | ALU | OP_ISYNC | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isync | XL |
0b0000010010 | TRAP | OP_RFID | SPR | SPR | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | rfid | XL |
0b0100010010 | TRAP | OP_RFID | SPR | SPR | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | hrfid | XL |
Minor opcode 30
decodes using f_in.insn(4 downto 1)
opcode | unit | internal op | in1 | in2 | in3 | out | CR in | CR out | inv A | inv out | cry in | cry out | ldst len | BR | sgn ext | upd | rsrv | 32b | sgn | rc | lk | sgl pipe | comment | form |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0b0100 | SHIFT_ROT | OP_RLC | NONE | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | rldic | MD |
0b0101 | SHIFT_ROT | OP_RLC | NONE | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | rldic | MD |
0b0000 | SHIFT_ROT | OP_RLCL | NONE | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | rldicl | MDS |
0b0001 | SHIFT_ROT | OP_RLCL | NONE | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | rldicl | MDS |
0b0010 | SHIFT_ROT | OP_RLCR | NONE | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | rldicr | MD |
0b0011 | SHIFT_ROT | OP_RLCR | NONE | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | rldicr | MD |
0b0110 | SHIFT_ROT | OP_RLC | RA | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | rldimi | MD |
0b0111 | SHIFT_ROT | OP_RLC | RA | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | rldimi | MD |
0b1000 | SHIFT_ROT | OP_RLCL | NONE | RB | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | rldcl | MD |
0b1001 | SHIFT_ROT | OP_RLCR | NONE | RB | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | rldcr | MD |
Minor opcode 31
decodes using f_in.insn(10 downto 1)
opcode | unit | internal op | in1 | in2 | in3 | out | CR in | CR out | inv A | inv out | cry in | cry out | ldst len | BR | sgn ext | upd | rsrv | 32b | sgn | rc | lk | sgl pipe | comment | form |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0b0100001010 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | add | XO |
0b1100001010 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | addo | XO |
0b0000001010 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | addc | XO |
0b1000001010 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | addco | XO |
0b0010001010 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | adde | XO |
0b1010001010 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | addeo | XO |
0b0011101010 | ALU | OP_ADD | RA | CONST_M1 | NONE | RT | NONE | CR0 | 0 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | addme | XO |
0b1011101010 | ALU | OP_ADD | RA | CONST_M1 | NONE | RT | NONE | CR0 | 0 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | addmeo | XO |
0b0011001010 | ALU | OP_ADD | RA | NONE | NONE | RT | NONE | CR0 | 0 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | addze | XO |
0b1011001010 | ALU | OP_ADD | RA | NONE | NONE | RT | NONE | CR0 | 0 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | addzeo | XO |
0b0000011100 | LOGICAL | OP_AND | RS | RB | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | and | X |
0b0000111100 | LOGICAL | OP_AND | RS | RB | NONE | RA | NONE | CR0 | 1 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | andc | X |
0b0011111100 | LOGICAL | OP_BPERM | RS | RB | NONE | RA | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | bpermd | X |
0b0000000000 | ALU | OP_CMP | RA | RB | NONE | NONE | NONE | BF | 1 | 0 | ONE | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | NONE | 0 | 0 | cmp | X |
0b0111111100 | LOGICAL | OP_CMPB | RS | RB | NONE | RA | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | cmpb | X |
0b0011100000 | ALU | OP_CMPEQB | RA | RB | NONE | NONE | NONE | BF | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | cmpeqb | X |
0b0000100000 | ALU | OP_CMP | RA | RB | NONE | NONE | NONE | BF | 1 | 0 | ONE | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | cmpl | X |
0b0011000000 | RA | RB | NONE | NONE | NONE | BF | cmprb | X | ||||||||||||||||
0b0000111010 | LOGICAL | OP_CNTZ | RS | NONE | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | cntlzd | X |
0b0000011010 | LOGICAL | OP_CNTZ | RS | NONE | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | cntlzw | X |
0b1000111010 | LOGICAL | OP_CNTZ | RS | NONE | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | cnttzd | X |
0b1000011010 | LOGICAL | OP_CNTZ | RS | NONE | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | cnttzw | X |
0b1011110011 | RT | darn | X | |||||||||||||||||||||
0b0001010110 | ALU | OP_NOP | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | dcbf | X |
0b0000110110 | ALU | OP_NOP | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | dcbst | X |
0b0100010110 | ALU | OP_NOP | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | dcbt | X |
0b0011110110 | ALU | OP_NOP | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | dcbtst | X |
0b1111110110 | MMU | OP_DCBZ | RA_OR_ZERO | RB | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | dcbz | X |
0b0110001001 | DIV | OP_DIVE | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | divdeu | XO |
0b1110001001 | DIV | OP_DIVE | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | divdeuo | XO |
0b0110001011 | DIV | OP_DIVE | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | divweu | XO |
0b1110001011 | DIV | OP_DIVE | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | divweuo | XO |
0b0110101001 | DIV | OP_DIVE | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | RC | 0 | 0 | divde | XO |
0b1110101001 | DIV | OP_DIVE | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | RC | 0 | 0 | divdeo | XO |
0b0110101011 | DIV | OP_DIVE | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 1 | RC | 0 | 0 | divwe | XO |
0b1110101011 | DIV | OP_DIVE | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 1 | RC | 0 | 0 | divweo | XO |
0b0111001001 | DIV | OP_DIV | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | divdu | XO |
0b1111001001 | DIV | OP_DIV | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | divduo | XO |
0b0111001011 | DIV | OP_DIV | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | divwu | XO |
0b1111001011 | DIV | OP_DIV | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | divwuo | XO |
0b0111101001 | DIV | OP_DIV | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | RC | 0 | 0 | divd | XO |
0b1111101001 | DIV | OP_DIV | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | RC | 0 | 0 | divdo | XO |
0b0111101011 | DIV | OP_DIV | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 1 | RC | 0 | 0 | divw | XO |
0b1111101011 | DIV | OP_DIV | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 1 | RC | 0 | 0 | divwo | XO |
0b0100011100 | LOGICAL | OP_XOR | RS | RB | NONE | RA | NONE | CR0 | 0 | 1 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | eqv | X |
0b1110111010 | ALU | OP_EXTS | RS | NONE | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | extsb | X |
0b1110011010 | ALU | OP_EXTS | RS | NONE | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | extsh | X |
0b1111011010 | ALU | OP_EXTS | RS | NONE | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | extsw | X |
0b1101111010 | SHIFT_ROT | OP_EXTSWSLI | NONE | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | extswsli | XS |
0b1101111011 | SHIFT_ROT | OP_EXTSWSLI | NONE | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | extswsli | XS |
0b1111010110 | ALU | OP_ICBI | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | icbi | X |
0b0000010110 | ALU | OP_NOP | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | icbt | X |
0b0000001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0000101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0001001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0001101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0010001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0010101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0011001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0011101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0100001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0100101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0101001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0101101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0110001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0110101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0111001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0111101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1000001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1000101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1001001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1001101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1010001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1010101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1011001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1011101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1100001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1100101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1101001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1101101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1110001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1110101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1111001111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b1111101111 | CR | OP_ISEL | RA_OR_ZERO | RB | NONE | RT | BC | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | isel | A |
0b0000110100 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 0 | 1 | 0 | 0 | NONE | 0 | 1 | lbarx | X |
0b1101010101 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | cix | 0 | 0 | 0 | NONE | 0 | 0 | lbzcix | X |
0b0001110111 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | lbzux | X |
0b0001010111 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lbzx | X |
0b0001010100 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 0 | 1 | 0 | 0 | NONE | 0 | 1 | ldarx | X |
0b1000010100 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 1 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | ldbrx | X |
0b1101110101 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | cix | 0 | 0 | 0 | NONE | 0 | 0 | ldcix | X |
0b0000110101 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | ldux | X |
0b0000010101 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | ldx | X |
0b0001110100 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | 0 | 1 | 0 | 0 | NONE | 0 | 1 | lharx | X |
0b0101110111 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 1 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | lhaux | X |
0b0101010111 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 1 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lhax | X |
0b1100010110 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 1 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lhbrx | X |
0b1100110101 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | cix | 0 | 0 | 0 | NONE | 0 | 0 | lhzcix | X |
0b0100110111 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | lhzux | X |
0b0100010111 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lhzx | X |
0b0000010100 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 0 | 1 | 0 | 0 | NONE | 0 | 1 | lwarx | X |
0b0101110101 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 1 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | lwaux | X |
0b0101010101 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 1 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lwax | X |
0b1000010110 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 1 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lwbrx | X |
0b1100010101 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | cix | 0 | 0 | 0 | NONE | 0 | 0 | lwzcix | X |
0b0000110111 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | lwzux | X |
0b0000010111 | LDST | OP_LOAD | RA_OR_ZERO | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lwzx | X |
0b1000000000 | mcrxr | X | ||||||||||||||||||||||
0b1001000000 | mcrxrx | X | ||||||||||||||||||||||
0b0000010011 | CR | OP_MFCR | NONE | NONE | NONE | RT | WHOLE_REG | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | mfcr/mfocrf | XFX |
0b0001010011 | TRAP | OP_MFMSR | NONE | NONE | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | mfmsr | X |
0b0101010011 | SPR | OP_MFSPR | SPR | NONE | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | mfspr | XFX |
0b0100001001 | DIV | OP_MOD | RA | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | modud | X |
0b0100001011 | DIV | OP_MOD | RA | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | NONE | 0 | 0 | moduw | X |
0b1100001001 | DIV | OP_MOD | RA | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | NONE | 0 | 0 | modsd | X |
0b1100001011 | DIV | OP_MOD | RA | RB | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 1 | NONE | 0 | 0 | modsw | X |
0b0010010000 | CR | OP_MTCRF | RS | NONE | NONE | NONE | WHOLE_REG | WHOLE_REG | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | mtcrf/mtocrf | XFX |
0b0010110010 | TRAP | OP_MTMSRD | RS | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | mtmsrd | X |
0b0010010010 | TRAP | OP_MTMSR | RS | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | mtmsr | X |
0b0111010011 | SPR | OP_MTSPR | RS | NONE | NONE | SPR | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | mtspr | XFX |
0b0001001001 | MUL | OP_MUL_H64 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | RC | 0 | 0 | mulhd | XO |
0b0000001001 | MUL | OP_MUL_H64 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | mulhdu | XO |
0b0001001011 | MUL | OP_MUL_H32 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 1 | RC | 0 | 0 | mulhw | XO |
0b0000001011 | MUL | OP_MUL_H32 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | mulhwu | XO |
0b1001001001 | MUL | OP_MUL_H64 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | RC | 0 | 0 | mulhd | XO |
0b1000001001 | MUL | OP_MUL_H64 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | mulhdu | XO |
0b1001001011 | MUL | OP_MUL_H32 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 1 | RC | 0 | 0 | mulhw | XO |
0b1000001011 | MUL | OP_MUL_H32 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | mulhwu | XO |
0b0011101001 | MUL | OP_MUL_L64 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | RC | 0 | 0 | mulld | XO |
0b1011101001 | MUL | OP_MUL_L64 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | RC | 0 | 0 | mulldo | XO |
0b0011101011 | MUL | OP_MUL_L64 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 1 | RC | 0 | 0 | mullw | XO |
0b1011101011 | MUL | OP_MUL_L64 | RA | RB | NONE | RT | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 1 | RC | 0 | 0 | mullwo | XO |
0b0111011100 | LOGICAL | OP_AND | RS | RB | NONE | RA | NONE | CR0 | 0 | 1 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | nand | X |
0b0001101000 | ALU | OP_ADD | RA | NONE | NONE | RT | NONE | NONE | 1 | 0 | ONE | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | neg | XO |
0b1001101000 | ALU | OP_ADD | RA | NONE | NONE | RT | NONE | NONE | 1 | 0 | ONE | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | nego | XO |
0b0001111100 | LOGICAL | OP_OR | RS | RB | NONE | RA | NONE | CR0 | 0 | 1 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | nor | X |
0b0110111100 | LOGICAL | OP_OR | RS | RB | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | or | X |
0b0110011100 | LOGICAL | OP_OR | RS | RB | NONE | RA | NONE | CR0 | 1 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | orc | X |
0b0001111010 | LOGICAL | OP_POPCNT | RS | NONE | NONE | RA | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | popcntb | X |
0b0111111010 | LOGICAL | OP_POPCNT | RS | NONE | NONE | RA | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | popcntd | X |
0b0101111010 | LOGICAL | OP_POPCNT | RS | NONE | NONE | RA | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | popcntw | X |
0b0010111010 | LOGICAL | OP_PRTY | RS | NONE | NONE | RA | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | prtyd | X |
0b0010011010 | LOGICAL | OP_PRTY | RS | NONE | NONE | RA | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | prtyw | X |
0b0010000000 | CR | OP_SETB | NONE | NONE | NONE | RT | BFA | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | setb | VX |
0b0111110010 | MMU | OP_TLBIE | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | slbia | X |
0b0000011011 | SHIFT_ROT | OP_SHL | NONE | RB | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | sld | X |
0b0000011000 | SHIFT_ROT | OP_SHL | NONE | RB | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | slw | X |
0b1100011010 | SHIFT_ROT | OP_SHR | NONE | RB | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | RC | 0 | 0 | srad | X |
0b1100111010 | SHIFT_ROT | OP_SHR | NONE | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | RC | 0 | 0 | sradi | XS |
0b1100111011 | SHIFT_ROT | OP_SHR | NONE | CONST_SH | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 1 | RC | 0 | 0 | sradi | XS |
0b1100011000 | SHIFT_ROT | OP_SHR | NONE | RB | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 1 | NONE | 0 | 0 | 0 | 0 | 1 | 1 | RC | 0 | 0 | sraw | X |
0b1100111000 | SHIFT_ROT | OP_SHR | NONE | CONST_SH32 | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 1 | NONE | 0 | 0 | 0 | 0 | 1 | 1 | RC | 0 | 0 | srawi | X |
0b1000011011 | SHIFT_ROT | OP_SHR | NONE | RB | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | srd | X |
0b1000011000 | SHIFT_ROT | OP_SHR | NONE | RB | RS | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | RC | 0 | 0 | srw | X |
0b1111010101 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | cix | 0 | 0 | 0 | NONE | 0 | 1 | stbcix | X |
0b1010110110 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | CR0 | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 0 | 1 | 0 | 0 | ONE | 0 | 1 | stbcx | X |
0b0011110111 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 1 | 0 | 0 | 0 | RC | 0 | 1 | stbux | X |
0b0011010111 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is1B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | stbx | X |
0b1010010100 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 1 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | stdbrx | X |
0b1111110101 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | cix | 0 | 0 | 0 | NONE | 0 | 1 | stdcix | X |
0b0011010110 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | CR0 | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 0 | 1 | 0 | 0 | ONE | 0 | 1 | stdcx | X |
0b0010110101 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | stdux | X |
0b0010010101 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | stdx | X |
0b1110010110 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 1 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | sthbrx | X |
0b1110110101 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | cix | 0 | 0 | 0 | NONE | 0 | 1 | sthcix | X |
0b1011010110 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | CR0 | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | 0 | 1 | 0 | 0 | ONE | 0 | 1 | sthcx | X |
0b0110110111 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | sthux | X |
0b0110010111 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is2B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | sthx | X |
0b1010010110 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 1 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | stwbrx | X |
0b1110010101 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | cix | 0 | 0 | 0 | NONE | 0 | 1 | stwcix | X |
0b0010010110 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | CR0 | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 0 | 1 | 0 | 0 | ONE | 0 | 1 | stwcx | X |
0b0010110111 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | stwux | X |
0b0010010111 | LDST | OP_STORE | RA_OR_ZERO | RB | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | stwx | X |
0b0000101000 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 1 | 0 | ONE | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | subf | XO |
0b1000101000 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 1 | 0 | ONE | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | subfo | XO |
0b0000001000 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 1 | 0 | ONE | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | subfc | XO |
0b1000001000 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 1 | 0 | ONE | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | subfco | XO |
0b0010001000 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 1 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | subfe | XO |
0b1010001000 | ALU | OP_ADD | RA | RB | NONE | RT | NONE | CR0 | 1 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | subfeo | XO |
0b0011101000 | ALU | OP_ADD | RA | CONST_M1 | NONE | RT | NONE | CR0 | 1 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | subfme | XO |
0b1011101000 | ALU | OP_ADD | RA | CONST_M1 | NONE | RT | NONE | CR0 | 1 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | subfmeo | XO |
0b0011001000 | ALU | OP_ADD | RA | NONE | NONE | RT | NONE | CR0 | 1 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | subfze | XO |
0b1011001000 | ALU | OP_ADD | RA | NONE | NONE | RT | NONE | CR0 | 1 | 0 | CA | 1 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | subfzeo | XO |
0b1001010110 | ALU | OP_NOP | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | sync | X |
0b0001000100 | TRAP | OP_TRAP | RA | RB | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | td | X |
0b0000000100 | TRAP | OP_TRAP | RA | RB | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 1 | 0 | NONE | 0 | 1 | tw | X |
0b0100110010 | MMU | OP_TLBIE | NONE | RB | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | tlbie | X |
0b0100010010 | MMU | OP_TLBIE | NONE | RB | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | tlbiel | X |
0b0100111100 | LOGICAL | OP_XOR | RS | RB | NONE | RA | NONE | CR0 | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 0 | xor | X |
Minor opcode 58
decodes using f_in.insn(1 downto 0)
opcode | unit | internal op | in1 | in2 | in3 | out | CR in | CR out | inv A | inv out | cry in | cry out | ldst len | BR | sgn ext | upd | rsrv | 32b | sgn | rc | lk | sgl pipe | comment | form |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | LDST | OP_LOAD | RA_OR_ZERO | CONST_DS | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | ld | DS |
1 | LDST | OP_LOAD | RA_OR_ZERO | CONST_DS | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | ldu | DS |
2 | LDST | OP_LOAD | RA_OR_ZERO | CONST_DS | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | is4B | 0 | 1 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | lwa | DS |
Minor opcode 62
decodes using f_in.insn(1 downto 0)
opcode | unit | internal op | in1 | in2 | in3 | out | CR in | CR out | inv A | inv out | cry in | cry out | ldst len | BR | sgn ext | upd | rsrv | 32b | sgn | rc | lk | sgl pipe | comment | form |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | LDST | OP_STORE | RA_OR_ZERO | CONST_DS | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | std | DS |
1 | LDST | OP_STORE | RA_OR_ZERO | CONST_DS | RS | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | is8B | 0 | 0 | 1 | 0 | 0 | 0 | NONE | 0 | 1 | stdu | DS |
Extra opcodes
These can match against the (full) row[0] spec: nmigen Case supports "-" as "don't care"
opcode | unit | internal op | in1 | in2 | in3 | out | CR in | CR out | inv A | inv out | cry in | cry out | ldst len | BR | sgn ext | upd | rsrv | 32b | sgn | rc | lk | sgl pipe | comment | form |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
000000---------------0100000000- | NONE | OP_ATTN | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | RC | 0 | 1 | attn | NONE |
01100000000000000000000000000000 | NONE | OP_NOP | NONE | NONE | NONE | NONE | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 0 | nop | D |
000001---------------0000000011- | NONE | OP_SIM_CONFIG | NONE | NONE | NONE | RT | NONE | NONE | 0 | 0 | ZERO | 0 | NONE | 0 | 0 | 0 | 0 | 0 | 0 | NONE | 0 | 1 | sim_cfg | NONE |
SPRs
Special Purpose Registers. These are listed in 3.0B Table 18 p971.
Idx | SPR | priv_mtspr | priv_mfspr | len |
---|---|---|---|---|
1 | XER | no | no | 64 |
3 | DSCR | no | no | 64 |
8 | LR | no | no | 64 |
9 | CTR | no | no | 64 |
13 | AMR | no | no | 64 |
17 | DSCR_priv | yes | yes | 64 |
18 | DSISR | yes | yes | 32 |
19 | DAR | yes | yes | 64 |
22 | DEC | yes | yes | 64 |
26 | SRR0 | yes | yes | 64 |
27 | SRR1 | yes | yes | 64 |
28 | CFAR | yes | yes | 64 |
29 | AMR_priv | yes | yes | 64 |
48 | PIDR | yes | yes | 32 |
61 | IAMR | yes | yes | 64 |
128 | TFHAR | no | no | 64 |
129 | TFIAR | no | no | 64 |
130 | TEXASR | no | no | 64 |
131 | TEXASRU | no | no | 32 |
136 | CTRL | - | no | 32 |
144 | TIDR | yes | yes | 64 |
152 | CTRL_priv | yes | - | 32 |
153 | FSCR | yes | yes | 64 |
157 | UAMOR | yes | yes | 64 |
158 | GSR | yes | - | 0 |
159 | PSPB | yes | yes | 32 |
176 | DPDES | hypv | yes | 64 |
180 | DAWR0 | hypv | hypv | 64 |
186 | RPR | hypv | hypv | 64 |
187 | CIABR | hypv | hypv | 64 |
188 | DAWRX0 | hypv | hypv | 32 |
190 | HFSCR | hypv | hypv | 64 |
256 | VRSAVE | no | no | 32 |
259 | SPRG3 | - | no | 64 |
268 | TB | - | no | 64 |
269 | TBU | - | no | 32 |
272 | SPRG0_priv | yes | yes | 64 |
273 | SPRG1_priv | yes | yes | 64 |
274 | SPRG2_priv | yes | yes | 64 |
275 | SPRG3_priv | yes | yes | 64 |
283 | CIR | - | yes | 32 |
284 | TBL | hypv | - | 32 |
285 | TBU_hypv | hypv | - | 32 |
286 | TBU40 | hypv | - | 64 |
287 | PVR | - | yes | 32 |
304 | HSPRG0 | hypv | hypv | 64 |
305 | HSPRG1 | hypv | hypv | 64 |
306 | HDSISR | hypv | hypv | 32 |
307 | HDAR | hypv | hypv | 64 |
308 | SPURR | hypv | yes | 64 |
309 | PURR | hypv | yes | 64 |
310 | HDEC | hypv | hypv | 64 |
313 | HRMOR | hypv | hypv | 64 |
314 | HSRR0 | hypv | hypv | 64 |
315 | HSRR1 | hypv | hypv | 64 |
318 | LPCR | hypv | hypv | 64 |
319 | LPIDR | hypv | hypv | 32 |
336 | HMER | hypv | hypv | 64 |
337 | HMEER | hypv | hypv | 64 |
338 | PCR | hypv | hypv | 64 |
339 | HEIR | hypv | hypv | 32 |
349 | AMOR | hypv | hypv | 64 |
446 | TIR | - | yes | 64 |
464 | PTCR | hypv | hypv | 64 |
704 | SVSTATE | no | no | 32 |
720 | PRTBL | yes | yes | 64 |
721 | SVSRR0 | yes | yes | 32 |
768 | SIER | - | no | 64 |
769 | MMCR2 | no | no | 64 |
770 | MMCRA | no | no | 64 |
771 | PMC1 | no | no | 32 |
772 | PMC2 | no | no | 32 |
773 | PMC3 | no | no | 32 |
774 | PMC4 | no | no | 32 |
775 | PMC5 | no | no | 32 |
776 | PMC6 | no | no | 32 |
779 | MMCR0 | no | no | 64 |
780 | SIAR | - | no | 64 |
781 | SDAR | - | no | 64 |
782 | MMCR1 | - | no | 64 |
784 | SIER_priv | yes | yes | 64 |
785 | MMCR2_priv | yes | yes | 64 |
786 | MMCRA_priv | yes | yes | 64 |
787 | PMC1_priv | yes | yes | 32 |
788 | PMC2_priv | yes | yes | 32 |
789 | PMC3_priv | yes | yes | 32 |
790 | PMC4_priv | yes | yes | 32 |
791 | PMC5_priv | yes | yes | 32 |
792 | PMC6_priv | yes | yes | 32 |
795 | MMCR0_priv | yes | yes | 64 |
796 | SIAR_priv | yes | yes | 64 |
797 | SDAR_priv | yes | yes | 64 |
798 | MMCR1_priv | yes | yes | 64 |
800 | BESCRS | no | no | 64 |
801 | BESCRSU | no | no | 32 |
802 | BESCRR | no | no | 64 |
803 | BESCRRU | no | no | 32 |
804 | EBBHR | no | no | 64 |
805 | EBBRR | no | no | 64 |
806 | BESCR | no | no | 64 |
808 | reserved808 | no | no | 0 |
809 | reserved809 | no | no | 0 |
810 | reserved810 | no | no | 0 |
811 | reserved811 | no | no | 0 |
815 | TAR | no | no | 64 |
816 | ASDR | hypv | hypv | 64 |
823 | PSSCR | yes | yes | 64 |
848 | IC | hypv | yes | 64 |
849 | VTB | hypv | yes | 64 |
855 | PSSCR_hypv | hypv | hypv | 64 |
896 | PPR | no | no | 64 |
898 | PPR32 | no | no | 32 |
1023 | PIR | - | yes | 32 |
Fields
These can be downloaded in plain text format here: fields.text