base+4 ... base+2 base number of bits
..xxxx xxxxxxxxxxxxxxxx xnnnxxxxx1111111 (80+16*nnn)-bit, nnn!=111
{ops}{Pred}{Reg}{VL Block} VBLOCK Prefix

A suitable prefix, which fits the Expanded Instruction-Length encoding for "(80 + 16 times instruction-length)", as defined in Section 1.5 of the RISC-V ISA, is as follows:

15 14:12 11:10 9 8 7 6:0
vlset 16xil rplen pplen pmode rmode 1111111

The VL/MAXVL/SubVL Block format, when 16xil != 0b111, is:

31:30 29:28 27:22 21 20:19 18:16 comment..................
0b00 SubVL imm[5:0] rsvd rd[4:0] sv.setvl rd, x0, imm
0b01 SubVL imm[5:0] rs1[2:0] rd[2:0] sv.setvl rd, rs1, imm (1)
0b10 SubVL imm[5:0] rsvd rs1[4:0] sv.setvl x0, rs1, imm
0b11 rsvd rsvd rsvd rsvd reserved, all 0s

Note (1) - Registers are in RVC format (x8-x15)

Note (2) - sv.setvl behaviour is expected, as if an sv.setvl instruction had actually been called.

When 16xil is 0b111, this is the "Extended" Format, using the >= 192-bit RISC-V ISA format. Note that the length is 96+16*nnnnn, not 192+

base+5 ... base+3 base+1 base no. of bits
..xxxx xxxxxxxxxxxxxxxx x111xxxxx1111111 96+16*nnnnn
{ops}{Pred}{Reg}{VL Block} VBLOCK2 VBLOCK Prefix

VBLOCK2 extends the VBLOCK fields:

15 14:12 11:10 9:8 7:5 4:0
rsvd mapsz rplen2 pplen2 swlen ilen

* ilen is the instruction length (number of 16-bit blocks) * swlen specifies the number of "swizzle" blocks * rplen2 extends rplen by 2 bits * pplen2 extends pplen by 2 bits * mapsz indicates the size of the "remap" area. See table below for size * 1 bit is reserved for extensions

Mapsz to Remap size is in number of 16-bit blocks:

mapsz remap size
0 0
1 6
2 7
3 8
4 10
5 12
6 14
7 16