Interfaces for the 180nm Oct2020 ASIC

List Link

Bugreport and discussion at https://bugs.libre-soc.org/show_bug.cgi?id=304

These are bare minimum viability: These should be easily doable with LiteX.

Under consideration:

Secondary priorities

  • a pinmux
  • USB - again doable with LiteX. I'm talking to Enjoy Digital about what USB PHYs LiteX supports. - Yehowshua
  • SERDES for Ethernet - using LiteX and Marvell PHY
  • Noting that a SERDES to RGMII PHY is $20 (kinda expensive for total cost of an SBC), we can instead do Eth over USB like the original RPI. This moves the complexity to software - could make doing eth things during boot loader a little more complex.

Jacob notes:

I haven't checked but I'm 99% sure that we will need to implement standard Power atomics, fences, ll/sc (including 128-bit version), cache flushes, and non-cacheable load/store operations if we want to support Linux on our october test chip.

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006407.html

Alternate USB Interface Options

  • https://github.com/im-tomu/valentyusb
  • https://github.com/lambdaconcept/lambdaUSB
  • https://github.com/greatscottgadgets/luna