Crypto-router ASIC

Specifications

All of these are entirely Libre-Licensed or are to be written as Libre-Licensed:

  • 300 mhz single-core, Libre-SOC OpenPOWER CPU with bitmanip extensions
  • 180/130 nm (TBD)
  • 5x RGMII Gigabit Ethernet PHYs with SRAM on-chip, built-in.
  • 2x USB ULPI PHYs
  • Direct DMA interface (independent bulk transfer)
  • JTAG, GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
  • On-board Dual-ported SRAM (for Packet Buffers)
  • Opencores sdram
  • Wishbone interfaces to all peripherals
  • XICS ICP / ICS Interrupt Controller

Example packet transfer

  • Packet comes in on RGMII port 1. Each PHY has its own dual-ported SRAM
  • Packet is directly stored in internal (dual-ported SRAM) by the RGMII PHY itself
  • Interrupt notification is sent to the processor (XICS)
  • Processor inspects packet over Wishbone interface directly connected to 2nd SRAM port.
  • Processor computes, based on decoding the ETH Frame, where the packet must be sent to (which other RGM-II port: e.g. Port 2)
  • Processor initiates Memory-to-Memory DMA transfer
  • DMA Memory-to-Memory transfer, using Wishbone Bus, copies the ETH Frame from one on-board SRAM to the target on-board SRAM associated with Port 2.
  • DMA Engine generates interrupt (XICS) to the CPU to say it is completed
  • Processor notifies target RGM-II PHY to activate "send" of frame out through target RGM-II port 2.

Testing and Verification

We will need full HDL simulations as well as post P&R simulations. These may be achieved as follows:

  • ISA-level unit tests as well as Formal Correctness Proofs. Example bpermd proof and individual unit tests for the Logical pipeline
  • Litex sim.py with some peripherals developed in c++ as verilator modules
  • nmigen-based OpenPOWER Libre-SOC core co-simulation such as this unit test, test_issuer.py
  • cocotb pre/post PnR including GHDL, Icarus and Verilator (where best suited)

Actual instructions being developed (bitmanip) may therefore be unit tested prior to deployment. Following that, rapid simulations may be achieved by running Litex (the same HDL may also easily be uploaded to an FPGA). When it comes to Place-and-Route of the ASIC, the cocotb simulations may be used to verify that the GDS-II layout has not been "damaged" by the PnR tools.

Peripherals functionality tests must also be part of the simulations, particularly using cocotb, to ensure that they remain functional after PnR. Supercomputer access for compilation of verilator and/or cxxrtl is available through fed4fire